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公开(公告)号：US20240411938A1
公开(公告)日：2024-12-12
申请号：US18813462
申请日：2024-08-23
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Theodore F. Emerson , Shiva R. Dasari , Luis E. Luciani, JR. , Kevin E. Boyum , Naysen J. Robertson , Robert L. Noonan , Christopher M. Wesneski , David F. Heinrich
Abstract: An apparatus includes a host and a baseboard management controller. The baseboard management controller includes a semiconductor package; and the semiconductor package includes a memory, a security hardware processor; and a main hardware processor. The main hardware processor causes the baseboard management controller to serve as an agent that, independently from the host, responds to communications with a remote management entity to manage the host. The security hardware processor manages the storage of a secret of the host in the memory.
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公开(公告)号：US12105859B2
公开(公告)日：2024-10-01
申请号：US17452722
申请日：2021-10-28
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Theodore F. Emerson , Shiva R. Dasari , Luis E. Luciani, Jr. , Kevin E. Boyum , Naysen J. Robertson , Robert L. Noonan , Christopher M. Wesneski , David F. Heinrich
CPC classification number: G06F21/78 , G06F21/33 , G06F21/53 , G06F21/602
Abstract: An apparatus includes a host and a baseboard management controller. The baseboard management controller includes a semiconductor package; and the semiconductor package includes a memory, a security hardware processor; and a main hardware processor. The main hardware processor causes the baseboard management controller to serve as an agent that, independently from the host, responds to communications with a remote management entity to manage the host. The security hardware processor manages the storage of a secret of the host in the memory.
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23.发明授权公开(公告)号：US11757612B2
公开(公告)日：2023-09-12
申请号：US17452823
申请日：2021-10-29
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： David F. Heinrich , Gennadiy Rozenberg , Scott P. Faasse , Melvin K. Benedict
CPC classification number: H04L7/0037 , H04L7/0012
Abstract: A process includes a port of a bridge providing a reference clock signal to a first end of an interconnect extending between the first port and a network interface controller. The reference clock signal propagates over the interconnect to provide, at a second end of the interconnect, a delayed reference clock signal at the network interface controller. Pursuant to the process, the bridge senses a timing of the delayed reference clock signal. The process includes communicating management traffic between a network interface of a baseboard management controller and the network interface controller via the interconnect. The communication of the management traffic includes the port, responsive to the sensing of the timing of the delayed reference clock signal, synchronizing communication of data with the first end of the interconnect to the delayed reference clock signal.
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公开(公告)号：US20230229132A1
公开(公告)日：2023-07-20
申请号：US17580398
申请日：2022-01-20
Applicant: Hewlett Packard Enterprise Development LP
Inventor： David F. Heinrich , Pranay Mahendra , Stephen Robert Jones , Gennadiy Rozenberg
IPC: G05B19/045 , G06F21/44 , G01R21/133
CPC classification number: G05B19/045 , G01R21/133 , G06F21/44 , G05B2219/25257
Abstract: A system is provided, which manages, by a microcontroller internal to a fan installed in a server, power data associated with the fan, wherein the fan includes two pins configured to communicate signals based on an inter-integrated circuit (I2C). During operation of the fan, the microcontroller measures a first and second amount of power consumed by the fan at a first and second time. The microcontroller transmits, via the two pins, the information to a system management entity which monitors and manages the server, wherein the system management entity controls a speed of the fan in response to receiving the measured power data and based on a net power comprising a difference between a total amount of power consumed by the server and an amount of power consumed by the fan.
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Patent Agency Ranking
公开(公告)号：US20210382841A1
公开(公告)日：2021-12-09
申请号：US16896863
申请日：2020-06-09
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Naysen J. Robertson , Robert L. Noonan , David F. Heinrich
Abstract: A processor executes firmware to write control data describing transfer descriptors for a bus protocol engine to an address that is associated with a transfer descriptor buffer for the bus protocol engine. The bus protocol engine performs an operation according to the transfer descriptors with a slave device; the processor is part of a first semiconductor package; the bus protocol engine is part of a second semiconductor package other than the first semiconductor package; and the address corresponds to a memory of the second semiconductor package. A first physical interface of the first semiconductor package communicates with a second physical interface of the second semiconductor package to direct the control data to the memory.
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公开(公告)号：US20210318941A1
公开(公告)日：2021-10-14
申请号：US16844443
申请日：2020-04-09
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： David F. Heinrich , Scott Faasse
IPC: G06F11/30 , G06F11/34 , G06F1/3206 , G06F9/50 , G06Q30/04
Abstract: Examples described herein relate to consumption monitoring device and method for changing a client for its use of a networked resource. The consumption monitoring device may receive information regarding an out-of-band (OOB) performance parameter from a manageability controller corresponding to a networked resource subscribed by the client. The consumption monitoring device may determine a resource consumption metric corresponding to the networked resource for the client based at least on the information regarding the OOB performance parameter received from the manageability controller. The client may be charged based on the resource consumption metric.
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公开(公告)号：US20200089290A1
公开(公告)日：2020-03-19
申请号：US16135307
申请日：2018-09-19
Applicant: Hewlett Packard Enterprise Development LP
Inventor： David F. Heinrich , Arthur Volkmann , Rachel Pollock
Abstract: An apparatus can include a fan including a control pin. The fan may receive a pulse width modulated (PWM) signal at the control pin. The fan may further control a speed of the fan based on a duty cycle of the PWM signal when the PWM signal is in a first range and, responsive to the duty cycle of the PWM signal being in a second range, transmit information corresponding to the fan to an external controller.
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公开(公告)号：US10372400B2
公开(公告)日：2019-08-06
申请号：US15565225
申请日：2015-05-21
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Theodore F. Emerson , David F. Heinrich , Kenneth T. Chin
IPC: G09G5/36 , G06F3/14 , H04N5/76 , G06T1/60 , H04N21/2365 , H04N21/242 , H04N21/426
Abstract: An apparatus includes a plurality of compute nodes and a baseboard management controller that is shared by the plurality of compute nodes to manage video for the compute nodes. The baseboard management controller includes video controllers that are associated with the plurality of compute nodes and at least one resource that is shared by the video controllers.
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公开(公告)号：US10275314B2
公开(公告)日：2019-04-30
申请号：US15523442
申请日：2014-11-20
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Matthew T Bolt , David F. Heinrich
Abstract: Example implementations relate to data transfer using backup power supply. For example, a system includes a shared backup power supply coupled to a node. The system also includes a controller to detect an interruption of primary power supply to the node and isolate a portion of the node from a sequenced shutdown of the node. The controller is further to initiate a transfer of data, utilizing the shared backup power supply, from volatile memory of the node to non-volatile memory of the node.
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