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公开(公告)号：US20240019490A1
公开(公告)日：2024-01-18
申请号：US17812937
申请日：2022-07-15
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Naysen J. Robertson , Christopher M. Wesneski , Samuel Gonzalez
IPC: G01R31/317 , G01R31/3185
CPC classification number: G01R31/31727 , G01R31/3185
Abstract: In some examples, a computing device includes a first reset domain including a test controller and a configurable test logic. The computing device includes a second reset domain including a subsystem to be measured by the configurable test logic. The first reset domain is to enter a reset mode, and after exiting the reset mode, receive configuration information that configures the configurable test logic. The test controller of the first reset domain is to maintain the second reset domain in a reset mode after the first reset domain has exited the reset mode of the first reset domain, and responsive to the received configuration information for configuring the configurable test logic, provide a reset release indication to the second reset domain to allow the second reset domain to exit the reset mode of the second reset domain.
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公开(公告)号：US20230134324A1
公开(公告)日：2023-05-04
申请号：US17452722
申请日：2021-10-28
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Theodore F. Emerson , Shiva R. Dasari , Luis E. Luciani, JR. , Kevin E. Boyum , Naysen J. Robertson , Robert L. Noonan , Christopher M. Wesneski , David F. Heinrich
Abstract: An apparatus includes a host and a baseboard management controller. The baseboard management controller includes a semiconductor package; and the semiconductor package includes a memory, a security hardware processor; and a main hardware processor. The main hardware processor causes the baseboard management controller to serve as an agent that, independently from the host, responds to communications with a remote management entity to manage the host. The security hardware processor manages the storage of a secret of the host in the memory.
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3.发明公开公开(公告)号：US20240168784A1
公开(公告)日：2024-05-23
申请号：US18058127
申请日：2022-11-22
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Naysen J. Robertson , Samuel Gonzalez , David A. Young , Theodore F. Emerson , Nathaniel W. Jansen
IPC: G06F9/455
CPC classification number: G06F9/45529
Abstract: A process includes emulating, by a programmable logic device, a hardware component to provide an emulated hardware component. The emulated hardware component is capable of exercising the predetermined functionality. The process includes testing the emulated hardware component. The process includes determining, by the programmable logic device, whether the emulated hardware component exercised the predetermined functionality during the test. The determination includes, responsive to the testing, detecting, by a state sequence detector of the programmable logic device, whether the emulated hardware component sequenced through a plurality of states associated with the predetermined functionality. The process includes, responsive to the detection of whether the emulated hardware component sequenced through the plurality of states, generating, by the programmable logic device, an indicator representing a coverage of the predetermined functionality by the testing.
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Patent Agency Ranking
公开(公告)号：US11899066B2
公开(公告)日：2024-02-13
申请号：US17812937
申请日：2022-07-15
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Naysen J. Robertson , Christopher M. Wesneski , Samuel Gonzalez
IPC: G01R31/3185 , G06F30/34 , G01R31/317
CPC classification number: G01R31/3185 , G06F30/34 , G01R31/31727
Abstract: In some examples, a computing device includes a first reset domain including a test controller and a configurable test logic. The computing device includes a second reset domain including a subsystem to be measured by the configurable test logic. The first reset domain is to enter a reset mode, and after exiting the reset mode, receive configuration information that configures the configurable test logic. The test controller of the first reset domain is to maintain the second reset domain in a reset mode after the first reset domain has exited the reset mode of the first reset domain, and responsive to the received configuration information for configuring the configurable test logic, provide a reset release indication to the second reset domain to allow the second reset domain to exit the reset mode of the second reset domain.
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公开(公告)号：US11210252B1
公开(公告)日：2021-12-28
申请号：US16896863
申请日：2020-06-09
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Naysen J. Robertson , Robert L. Noonan , David F. Heinrich
Abstract: A processor executes firmware to write control data describing transfer descriptors for a bus protocol engine to an address that is associated with a transfer descriptor buffer for the bus protocol engine. The bus protocol engine performs an operation according to the transfer descriptors with a slave device; the processor is part of a first semiconductor package; the bus protocol engine is part of a second semiconductor package other than the first semiconductor package; and the address corresponds to a memory of the second semiconductor package. A first physical interface of the first semiconductor package communicates with a second physical interface of the second semiconductor package to direct the control data to the memory.
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公开(公告)号：US20240411938A1
公开(公告)日：2024-12-12
申请号：US18813462
申请日：2024-08-23
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Theodore F. Emerson , Shiva R. Dasari , Luis E. Luciani, JR. , Kevin E. Boyum , Naysen J. Robertson , Robert L. Noonan , Christopher M. Wesneski , David F. Heinrich
Abstract: An apparatus includes a host and a baseboard management controller. The baseboard management controller includes a semiconductor package; and the semiconductor package includes a memory, a security hardware processor; and a main hardware processor. The main hardware processor causes the baseboard management controller to serve as an agent that, independently from the host, responds to communications with a remote management entity to manage the host. The security hardware processor manages the storage of a secret of the host in the memory.
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公开(公告)号：US12105859B2
公开(公告)日：2024-10-01
申请号：US17452722
申请日：2021-10-28
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Theodore F. Emerson , Shiva R. Dasari , Luis E. Luciani, Jr. , Kevin E. Boyum , Naysen J. Robertson , Robert L. Noonan , Christopher M. Wesneski , David F. Heinrich
CPC classification number: G06F21/78 , G06F21/33 , G06F21/53 , G06F21/602
Abstract: An apparatus includes a host and a baseboard management controller. The baseboard management controller includes a semiconductor package; and the semiconductor package includes a memory, a security hardware processor; and a main hardware processor. The main hardware processor causes the baseboard management controller to serve as an agent that, independently from the host, responds to communications with a remote management entity to manage the host. The security hardware processor manages the storage of a secret of the host in the memory.
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公开(公告)号：US20210382841A1
公开(公告)日：2021-12-09
申请号：US16896863
申请日：2020-06-09
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Naysen J. Robertson , Robert L. Noonan , David F. Heinrich
Abstract: A processor executes firmware to write control data describing transfer descriptors for a bus protocol engine to an address that is associated with a transfer descriptor buffer for the bus protocol engine. The bus protocol engine performs an operation according to the transfer descriptors with a slave device; the processor is part of a first semiconductor package; the bus protocol engine is part of a second semiconductor package other than the first semiconductor package; and the address corresponds to a memory of the second semiconductor package. A first physical interface of the first semiconductor package communicates with a second physical interface of the second semiconductor package to direct the control data to the memory.
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