公开(公告)号：US20230261107A1

公开(公告)日：2023-08-17

申请号：US17672332

申请日：2022-02-15

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Wilfred Gomes ,  Sagar Suthram ,  Pushkar Sharad Ranade ,  Willy Rachmady ,  Ravi Pillarisetty ,  Anand S. Murthy

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/40 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/78391 ,  H01L29/516 ,  H01L29/401 ,  H01L29/7851 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696

Abstract: Disclosed herein are transistor gate-channel arrangements with transistor gate stacks that include dipole layers, and related methods and devices. Transistor gate stacks disclosed herein include a multilayer gate oxide having both a high-k dielectric and a dipole layer. In some embodiments, a thin dipole layer may directly border a channel material of choice and may be between the channel material and the high-k dielectric. In other embodiments, a passivation layer may spontaneously form between the dipole layer and the channel material. In still other embodiments, the high-k dielectric may be between the dipole layer and the channel material. Temporary polarization provided by the dipole layer may increase the effective dielectric constant of the high-k dielectric and may allow to use thinner high-k dielectrics and/or high-k dielectrics of suboptimal quality while maintaining transistor performance in terms of, e.g., gate leakage, carrier mobility, and subthreshold swing.

公开(公告)号：US11721735B2

公开(公告)日：2023-08-08

申请号：US17580550

申请日：2022-01-20

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Aaron Lilak ,  Van H. Le ,  Abhishek A. Sharma ,  Tahir Ghani ,  Willy Rachmady ,  Rishabh Mehandru ,  Nazila Haratipour ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Seung Hoon Sung ,  Shriram Shivaraman

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/4236 ,  H01L21/823412 ,  H01L21/823437 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696 ,  H01L29/66545

Abstract: Thin film transistors having U-shaped features are described. In an example, integrated circuit structure including a gate electrode above a substrate, the gate electrode having a trench therein. A channel material layer is over the gate electrode and in the trench, the channel material layer conformal with the trench. A first source or drain contact is coupled to the channel material layer at a first end of the channel material layer outside of the trench. A second source or drain contact is coupled to the channel material layer at a second end of the channel material layer outside of the trench.

公开(公告)号：US20230200080A1

公开(公告)日：2023-06-22

申请号：US17558419

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Wilfred Gomes ,  Uygar Avci

IPC: H01L27/11514 ,  G11C11/22 ,  H01L27/11504

CPC classification number: H01L27/11514 ,  G11C11/221 ,  H01L27/11504

Abstract: Three-dimensional ferroelectric memory cell architectures are discussed related to improved memory cell performance and density. Such three-dimensional ferroelectric memory cell architectures include groups of vertically stacked transistors accessed by vertical bit lines and horizontal word lines. Groups of such stacks of transistors are arrayed laterally. Adjacent transistor stacks are separated by isolation material or memory structures inclusive of capacitor structures or plate line structures.

公开(公告)号：US20230180482A1

公开(公告)日：2023-06-08

申请号：US17543809

申请日：2021-12-07

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Uygar E. Avci ,  Abhishek A. Sharma

IPC: H01L27/11514 ,  H01L27/11504 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/11514 ,  H01L27/11504 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

Abstract: Three-dimensional hysteretic memory based on semiconductor nanoribbons is disclosed. An example memory cell may include a nanoribbon-based access transistor and a capacitor coupled to the access transistor, where the capacitor at least partially wraps around the nanoribbon in which the access transistor is formed. One or both of a gate stack of the access transistor and the capacitor insulator may include a hysteretic material/arrangement. Plurality of such memory cells may be provided in a single nanoribbon, and the nanoribbon may be one of a stack of nanoribbons provided above one another over a support structure. Incorporating hysteretic memory cells in different layers above a support structure by using stacks of semiconductor nanoribbons may allow significantly increasing density of hysteretic memory cells in a memory array having a given footprint area, or conversely, significantly reducing the footprint area of the memory array with a given density of hysteretic memory cells.

公开(公告)号：US11652606B2

公开(公告)日：2023-05-16

申请号：US16140918

申请日：2018-09-25

Applicant: INTEL CORPORATION

Inventor： Abhishek A. Sharma ,  Willy Rachmady ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Jack T. Kavalieros

IPC: H04L9/06 ,  H04L9/08 ,  G06F9/30 ,  G06F12/0875 ,  G06F3/06 ,  G06F12/0862

CPC classification number: H04L9/0631 ,  G06F3/0623 ,  G06F9/30007 ,  G06F12/0862 ,  G06F12/0875 ,  H04L9/0816

Abstract: A stacked-substrate advanced encryption standard (AES) integrated circuit device is described in which at least some circuits associated logic functions (e.g., AES encryption operations, memory cell access and control) are provided on a first substrate. Memory arrays used with the AES integrated circuit device (sometimes referred to as “embedded memory”) are provided on a second substrate stacked on the first substrate, thus forming a AES integrated circuit device on a stacked-substrate assembly. Vias are fabricated to pass through the second substrate, into a dielectric layer between the first substrate and the second substrate, and electrically connect to conductive interconnections of the AES logic circuits.

公开(公告)号：US20230102219A1

公开(公告)日：2023-03-30

申请号：US17478720

申请日：2021-09-17

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  Matthew V. Metz ,  Hui Jae Yoo ,  Justin R. Weber ,  Van H. Le ,  Jason C. Retasket ,  Abhishek A. Sharma ,  Noriyuki Sato ,  Yu-Jin Chen ,  Eric Mattson ,  Edward O. Johnson, JR.

IPC: H01L29/45 ,  H01L29/786 ,  H01L29/78 ,  H01L29/66 ,  H01L27/108 ,  H01L29/417

Abstract: Described herein are integrated circuit devices with metal-oxide semiconductor channels and carbon source and drain (S/D) contacts. S/D contacts conduct current to and from the semiconductor devices, e.g., to the source and drain regions of a transistor. Carbon S/D contacts may be particularly useful with semiconductor devices that use certain channel materials, such as indium gallium zinc oxide.

公开(公告)号：US20220399342A1

公开(公告)日：2022-12-15

申请号：US17347735

申请日：2021-06-15

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Wilfred Gomes ,  Mauro J. Kobrinsky ,  Van H. Le

IPC: H01L27/108 ,  H01L27/092 ,  H01L29/66

Abstract: Described herein are three-dimensional transistors with a recessed gate, and IC devices including such three-dimensional transistors with recessed gates. The transistor includes a channel material having a recess. The channel material is formed over a support structure, and source/drain regions are formed in or on the channel material, e.g., one either side of the recess. A gate stack extends through the recess. The distance between the gate stack and the support structure is smaller than the distance between one of the source/drain regions and the support structure. This arrangement increases the channel length relative to prior art transistors, reducing leakage.

公开(公告)号：US20220399310A1

公开(公告)日：2022-12-15

申请号：US17345369

申请日：2021-06-11

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Wilfred Gomes ,  Mauro J. Kobrinsky ,  Doug B. Ingerly ,  Van H. Le

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L23/48 ,  H01L21/768 ,  H01L25/00

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing with modified via-last process are disclosed. The fabrication approach is based on using hybrid manufacturing to bond first and second IC structures originally provided on different dies but filling at least portions of vias that are supposed to couple across a bonding interface between the first and second IC structures with electrically conductive materials after the IC structures have been bonded. A resulting microelectronic assembly that includes the first and second IC structures bonded together may have vias extending through all of the first IC structure and into the second IC structure, thus providing electrical coupling between one or more components of the first IC structure and those of the second IC structure, where an electrically conductive material in the individual vias is continuous through the first IC structure and at least a portion of the second IC structure.

公开(公告)号：US11522059B2

公开(公告)日：2022-12-06

申请号：US15899590

申请日：2018-02-20

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Jack T. Kavalieros ,  Gilbert W. Dewey ,  Van H. Le ,  Lawrence D. Wong ,  Christopher J. Jezewski

IPC: H01L29/417 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/45 ,  H01L23/29 ,  H01L29/24 ,  H01L29/22

Abstract: Disclosed herein are transistor electrode-channel arrangements, and related methods and devices. For example, in some embodiments, a transistor electrode-channel arrangement may include a channel material, source/drain electrodes provided over the channel material, and a sealant at least partially enclosing one or more of the source/drain electrodes, wherein the sealant includes one or more metallic conductive materials.

公开(公告)号：US11444204B2

公开(公告)日：2022-09-13

申请号：US15939081

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Van H. Le ,  Sean T. Ma ,  Jack Kavalieros ,  Benjamin Chu-Kung

IPC: H01L29/786 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L27/12

Abstract: Techniques and mechanisms for improved performance characteristics of a transistor device. In an embodiment, a transistor of an integrated circuit comprises a source, a drain, a gate, a gate dielectric and a semiconductor structure which adjoins the gate dielectric. The semiconductor structure is configured to provide a conductive channel between the source and drain. The semiconductor structure includes first, second and third portions, the second portion between the source and the gate, and the third portion between the drain and the gate, wherein the first portion connects the second portion and third portion to one another. A thickness of the first portion is less than another thickness of one of the second portion or the third portion. In another embodiment, the locations of thicker portions of semiconductor structure mitigate overall transistor capacitance, while a thinner intermediary portion of the semiconductor structure promotes good sub-threshold swing characteristics.