公开(公告)号：US09313141B2

公开(公告)日：2016-04-12

申请号：US13771839

申请日：2013-02-20

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Sujoy Sen ,  Partha Sarangam

IPC: G06F15/16 ,  H04L12/863 ,  H04L12/859 ,  H04L12/861 ,  H04L29/06 ,  H04L12/28 ,  H04L29/08

CPC classification number: H04L47/622 ,  H04L47/2475 ,  H04L49/90 ,  H04L49/9047 ,  H04L49/9063 ,  H04L49/9094 ,  H04L69/12 ,  H04L69/32

Abstract: In general, in one aspect, computer program instructions are to cause, when executed, at least one processor to determine a transmit queue from many transmit queues to associate with a connection, store an identifier of the transmit queue in a connection socket structure associated with the connection, and access the identifier of the transmit queue from a connection socket structure associated with a connection of an egress packet.

Abstract translation: 通常，在一个方面，计算机程序指令在被执行时使得至少一个处理器确定来自许多发送队列的发送队列以与连接相关联，将发送队列的标识符存储在与 连接，并从与出口分组的连接相关联的连接套接字结构访问发送队列的标识符。

公开(公告)号：US20230421512A1

公开(公告)日：2023-12-28

申请号：US18243896

申请日：2023-09-08

Applicant: Intel Corporation

Inventor： Eliezer Tamir ,  Jesse C. Brandeburg ,  Anil Vasudevan

IPC: H04L49/90 ,  G06F9/48 ,  G06F9/52 ,  H04L49/901

CPC classification number: H04L49/90 ,  G06F9/4812 ,  G06F9/526 ,  H04L49/901 ,  G06F9/327

Abstract: Generally, this disclosure provides devices, methods, and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.

公开(公告)号：US11843550B2

公开(公告)日：2023-12-12

申请号：US17505443

申请日：2021-10-19

Applicant: Intel Corporation

Inventor： Eliezer Tamir ,  Jesse C. Brandeburg ,  Anil Vasudevan

IPC: H04L49/90 ,  G06F9/48 ,  G06F9/52 ,  H04L49/901 ,  G06F9/448 ,  G06F9/32

CPC classification number: H04L49/90 ,  G06F9/4812 ,  G06F9/526 ,  H04L49/901 ,  G06F9/327 ,  G06F9/4498

Abstract: Generally, this disclosure provides devices, methods, and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.

公开(公告)号：US11657015B2

公开(公告)日：2023-05-23

申请号：US17153751

申请日：2021-01-20

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Anil Vasudevan ,  David Harriman

IPC: G06F13/16 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4282 ,  G06F13/4072

Abstract: A device is provided with two or more uplink ports to connect the device via two or more links to one or more sockets, where each of the sockets includes one or more processing cores, and each of the two or more links is compliant with a particular interconnect protocol. The device further includes I/O logic to identify data to be sent to the one or more processing cores for processing, determine an affinity attribute associated with the data, and determine which of the two or more links to use to send the data to the one or more processing cores based on the affinity attribute.

公开(公告)号：US11502952B2

公开(公告)日：2022-11-15

申请号：US15969017

申请日：2018-05-02

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Parthasarathy Sarangam ,  Eric Mann ,  Daniel Cohn

IPC: H04L1/00 ,  H04L45/74 ,  H04L47/11 ,  H04L47/52 ,  H04L47/50 ,  H04L45/00

Abstract: Devices and techniques for reorder resilient transport are described herein. A device may store data packets in sequential positions of a flow queue in an order in which the data packets were received. The device may retrieve a first data packet from a first sequential position and a second data packet from a second sequential position that is next in sequence to the first sequential position in the flow queue. The device may store the first data packet and the second data packet in a buffer and refrain from providing the first data packet and the second data packet to upper layer circuitry if the packet order information for the first data packet and the second data packet indicate that the first data packet and the second data packet were received out of order. Other embodiments are also described.

公开(公告)号：US20220038395A1

公开(公告)日：2022-02-03

申请号：US17505443

申请日：2021-10-19

Applicant: Intel Corporation

Inventor： Eliezer Tamir ,  Jesse C. Brandeburg ,  Anil Vasudevan

IPC: H04L12/861 ,  G06F9/48 ,  G06F9/52 ,  H04L12/879

Abstract: Generally, this disclosure provides devices, methods, and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.

公开(公告)号：US11178076B2

公开(公告)日：2021-11-16

申请号：US16577406

申请日：2019-09-20

Applicant: INTEL CORPORATION

Inventor： Eliezer Tamir ,  Jesse C. Brandeburg ,  Anil Vasudevan

IPC: H04L12/861 ,  H04L12/879 ,  G06F9/48 ,  G06F9/52 ,  G06F9/448 ,  G06F9/32

Abstract: Generally, this disclosure provides devices, methods, and computer readable media for packet processing with reduced latency. The device may include a data queue to store data descriptors associated with data packets, the data packets to be transferred between a network and a driver circuit. The device may also include an interrupt generation circuit to generate an interrupt to the driver circuit. The interrupt may be generated in response to a combination of an expiration of a delay timer and a non-empty condition of the data queue. The device may further include an interrupt delay register to enable the driver circuit to reset the delay timer, the reset postponing the interrupt generation.

公开(公告)号：US20200285578A1

公开(公告)日：2020-09-10

申请号：US16822939

申请日：2020-03-18

Applicant: Intel Corporation

Inventor： Ren Wang ,  Joseph Nuzman ,  Samantika S. Sury ,  Andrew J. Herdrich ,  Namakkal N. Venkatesan ,  Anil Vasudevan ,  Tsung-Yuan C. Tai ,  Niall D. McDonnell

IPC: G06F12/0831 ,  G06F12/084 ,  G06F12/0811

Abstract: Apparatus, method, and system for implementing a software-transparent hardware predictor for core-to-core data communication optimization are described herein. An embodiment of the apparatus includes a plurality of hardware processor cores each including a private cache; a shared cache that is communicatively coupled to and shared by the plurality of hardware processor cores; and a predictor circuit. The predictor circuit is to track activities relating to a plurality of monitored cache lines in the private cache of a producer hardware processor core (producer core) and to enable a cache line push operation upon determining a target hardware processor core (target core) based on the tracked activities. An execution of the cache line push operation is to cause a plurality of unmonitored cache lines in the private cache of the producer core to be moved to the private cache of the target core.

公开(公告)号：US20190272124A1

公开(公告)日：2019-09-05

申请号：US16418405

申请日：2019-05-21

Applicant: INTEL CORPORATION

Inventor： Anil Vasudevan ,  Dave B. Minturn ,  Kiran Patil

IPC: G06F3/06

Abstract: Examples are disclosed for moving data between a network input/output (I/O) device and a storage subsystem and/or storage device. In some examples, a network I/O device coupled to a host device may receive a data frame including a request to access a storage subsystem or storage device. The storage subsystem and/or storage device may be located with the network I/O device or separately coupled to the host device through a storage controller. One or more buffers maintained in a cache for processor circuitry may be used to exchange control information or stage data associated with the data frame to avoid or eliminate use of system memory to move data to or from the storage subsystem and/or storage device. Other examples are described and claimed.

公开(公告)号：US20190004958A1

公开(公告)日：2019-01-03

申请号：US15640060

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Anil Vasudevan ,  Venkata Krishnan ,  Andrew J. Herdrich ,  Ren Wang ,  Robert G. Blankenship ,  Vedaraman Geetha ,  Shrikant M. Shah ,  Marshall A. Millier ,  Raanan Sade ,  Binh Q. Pham ,  Olivier Serres ,  Chyi-Chang Miao ,  Christopher B. Wilkerson

IPC: G06F12/0868 ,  G06F12/0811 ,  G06F3/06 ,  G06F12/0871

Abstract: Method and system for performing data movement operations is described herein. One embodiment of a method includes: storing data for a first memory address in a cache line of a memory of a first processing unit, the cache line associated with a coherency state indicating that the memory has sole ownership of the cache line; decoding an instruction for execution by a second processing unit, the instruction comprising a source data operand specifying the first memory address and a destination operand specifying a memory location in the second processing unit; and responsive to executing the decoded instruction, copying data from the cache line of the memory of the first processing unit as identified by the first memory address, to the memory location of the second processing unit, wherein responsive to the copy, the cache line is to remain in the memory and the coherency state is to remain unchanged.