公开(公告)号：US20240027697A1

公开(公告)日：2024-01-25

申请号：US17871558

申请日：2022-07-22

Applicant: Intel Corporation

Inventor： Wesley B. Morgan ,  Mohanraj Prabhugoud ,  David Shia ,  Eric J. M. Moret ,  Pooya Tadayon ,  Tarek A. Ibrahim

IPC: G02B6/38

CPC classification number: G02B6/3897 ,  G02B6/3885 ,  G02B6/3893

Abstract: Optical connectors with alignment features, and methods of forming the same, are disclosed herein. In one example, an optical ferrule includes holes to couple a fiber array to the optical ferrule, a mating protrusion to mate with an optical receptacle, and alignment features to align the fiber array with optical waveguides in the optical receptacle. The optical receptacle includes the optical waveguides, a mating cavity to mate with the mating protrusion on the optical ferrule, and alignment features to mate with the alignment features on the optical ferrule.

公开(公告)号：US20230137684A1

公开(公告)日：2023-05-04

申请号：US17517348

申请日：2021-11-02

Applicant: Intel Corporation

Inventor： Jin Yang ,  David Shia ,  Jimmy Chuang

IPC: H01L23/427 ,  H01L23/373

Abstract: A two-phase immersion cooling system for integrated circuit assemblies may be formed utilizing a heat dissipation assembly thermally coupled to at least one integrated circuit device, wherein the heat dissipation assembly includes a heat dissipation device having a boiling enhancement structure attached thereto with a chemically soluble adhesive material; and a thermal interface material between the boiling enhancement structure and the heat dissipation device. Utilizing a chemically soluble adhesive material allows for the boiling enhancement structure to be removed by dissolving the adhesive material, thus allowing for testing, rework, and/or replacement.

公开(公告)号：US11262384B2

公开(公告)日：2022-03-01

申请号：US16461387

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Pooya Tadayon ,  David Shia

IPC: G01R1/073 ,  G01R31/28

Abstract: An embodiment includes an apparatus comprising: a substrate including a surface that comprises first, second, and third apertures; and first, second, and third probes comprising proximal ends that are respectively included within and project from the first, second, and third apertures; wherein the first, second, and third probes: (a)(i) intersect a plane that is generally coplanar with the surface, (a)(ii) include distal ends configured to contact electrical contacts of a device under test (DUT), and (a)(iii) are generally linear and each include a major axis that is non-orthogonal to the plane. Other embodiments are described herein.

公开(公告)号：US20160274148A1

公开(公告)日：2016-09-22

申请号：US15165984

申请日：2016-05-26

Applicant: Intel Corporation

Inventor： Kip Stevenson ,  Todd P. Albertson ,  David Shia ,  Kamil Salloum

IPC: G01R1/067 ,  G01R31/26

CPC classification number: G01R1/06755 ,  G01R3/00 ,  G01R31/26 ,  G01R31/2886

Abstract: An examples includes a substrate, including a conductive trace and a layer disposed on top of the conductive trace, the layer defining at least one cavity extending to the conductive trace and an electrical probe disposed in the cavity, with solder coupling the electrical probe to the conductive trace. The electrical probe can include a high yield strength wire core including a refractory metal and a thin oxidation protection layer concentrically disposed around high yield strength wire core and providing an outside surface of the electrical probe, the thin oxidation protection layer including predominantly one or more materials selected from gold, platinum, ruthenium, rhodium, palladium, osmium, iridium, chromium, and combinations thereof, wherein the solder fills the cavity and is coupled to the electrical probe inside the cavity, disposed between the electrical probe and the layer.

Abstract translation: 示例包括基板，其包括导电迹线和设置在导电迹线顶部上的层，该层限定延伸到导电迹线的至少一个空腔和设置在该空腔中的电探针，其中焊料将电探针耦合到 导电痕迹 电探针可以包括高屈服强度的线芯，包括耐火金属和同心地设置在高屈服强度线芯周围的薄氧化保护层，并提供电探针的外表面，薄氧化保护层主要包括一种或多种材料 选自金，铂，钌，铑，钯，锇，铱，铬及其组合，其中焊料填充空腔并且耦合到设置在电探针和层之间的腔内的电探针。

公开(公告)号：US20250102745A1

公开(公告)日：2025-03-27

申请号：US18475907

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Mohanraj Prabhugoud ,  David Shia ,  Hari Mahalingam ,  John M. Heck ,  John Robert Macdonald ,  Duncan Peter Dore ,  Eric J. M. Moret ,  Nicholas D. Psaila ,  Sang Yup Kim ,  Shane Kevin Yerkes ,  Harel Frish

IPC: G02B6/42

Abstract: In one embodiment, a device includes a fiber array unit (FAU) coupled to a photonics integrated circuit (PIC) die. The PIC die includes a cavity defined at an edge of the PIC die, with outer edges of the cavity being formed at an angle less than 90 degrees with respect to a bottom surface of the cavity. The PIC die further includes first waveguides protruding into the cavity of the PIC die. The FAU includes a shelf portion extending from a body portion, and a plurality of second waveguides protruding from an outer edge of the shelf portion opposite the body portion. The FAU further includes alignment structures on outer edges of the shelf portion that are in contact with the angled edges of the cavity of the PIC die.

公开(公告)号：US20250004225A1

公开(公告)日：2025-01-02

申请号：US18345106

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Mohanraj Prabhugoud ,  David Shia ,  Tarek A. Ibrahim ,  Yuxin Fang

IPC: G02B6/42

Abstract: Technologies for substrate features for a pluggable optical connectors in an integrated circuit package are disclosed. In the illustrative embodiment, a substrate includes a cavity cut through a substrate of the integrated circuit package. Sidewalls of the cavity establish coarse lateral alignment features for an optical plug. The optical plug and optical socket include additional alignment features to more precisely align optical fibers in the optical plug to an optical interposer mounted on the substrate. The cavity cut through the substrate may also include indents that can mate with protrusions of the optical plug to retain the optical plug. The optical interposer may be mounted on a recessed shelf in the substrate.

公开(公告)号：US20240027706A1

公开(公告)日：2024-01-25

申请号：US17871473

申请日：2022-07-22

Applicant: Intel Corporation

Inventor： Pooya Tadayon ,  Eric J. M. Moret ,  Tarek A. Ibrahim ,  David Shia ,  Nicholas D. Psaila ,  Russell Childs

IPC: G02B6/42 ,  G02B6/43

CPC classification number: G02B6/4249 ,  G02B6/43 ,  G02B6/4214 ,  G02B6/4292

Abstract: In one embodiment, an integrated circuit device includes a substrate, an electronic integrated circuit (EIC), a photonics integrated circuit (PIC) electrically coupled to the EIC, and a glass block at least partially in a cavity defined by the substrate and at an end of the substrate. The glass block defines an optical path with one or more optical elements to direct light between the PIC and a fiber array unit (FAU) when attached to the glass block.

公开(公告)号：US11842943B2

公开(公告)日：2023-12-12

申请号：US16986122

申请日：2020-08-05

Applicant: Intel Corporation

Inventor： Barrett M. Faneuf ,  Phil Geng ,  Kenan Arik ,  David Shia ,  Casey Winkel ,  Sandeep Ahuja ,  Eric D. McAfee ,  Jeffory L. Smalley ,  Minh T. D. Le ,  Ralph V. Miele ,  Marc Milobinski ,  Aaron P. Anderson ,  Brendan T. Pavelek ,  Fernando Gonzalez Lenero ,  Carlos Alvizo Flores

IPC: H01L23/367 ,  H05K7/20 ,  H05K7/14 ,  G11C5/06

CPC classification number: H01L23/3677 ,  G11C5/06 ,  H05K7/1422 ,  H05K7/20509

Abstract: An apparatus is described. The apparatus includes an electronic system. The electronic system includes a chassis. The electronic system includes a semiconductor chip cooling component that is rigidly fixed to the chassis. The electronic system includes a packaged semiconductor chip having a lid that is contact with the semiconductor chip cooling component. The electronic system includes an electronic circuit board. The packaged semiconductor chip is electro-mechanically attached to the electronic circuit board.

公开(公告)号：US20210216121A1

公开(公告)日：2021-07-15

申请号：US17214230

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Kristin L. Weldon ,  David Rodriguez ,  Jin Yang ,  David Shia ,  Jimmy Chuang ,  Mohanraj Prabhugoud ,  Mark Edmund Sprenger

IPC: G06F1/20 ,  H05K7/20

Abstract: Techniques for liquid cooling interfaces with rotatable connector assemblies are disclosed. In one embodiment, a collar contacts flanges on two components of a connector assembly, preventing them from separating. In another embodiment, a housing is positioned around a stem component. The stem component has a gap between a top part and a bottom part held apart by pillars, allowing water to flow to a tubing fitting connected to the housing. A retainer on top of the stem component holds the housing in place. In yet another embodiment, an internal retainer holds a housing component in place over a stem. Other embodiments are disclosed.

公开(公告)号：US10595439B2

公开(公告)日：2020-03-17

申请号：US16017731

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： David Shia ,  Evan Chenelly ,  Mohanraj Prabhugoud

IPC: H05K7/20 ,  F28D15/02 ,  H05K1/18 ,  H05K1/02 ,  G06F1/20 ,  H01L23/427 ,  F28F1/30 ,  H01L23/467 ,  H01L23/367

Abstract: Embodiments described herein may include apparatuses, systems and/or processes to provide a cooling apparatus that includes a first heatsink, a second movable heatsink and a flexible thermal conductor physically and thermally coupled with the first and second heatsinks, where the flexible thermal conductor is to flex and remain thermally coupled with the first heatsink and the second heatsink, when the second heatsink is moved relative to the first heatsink. The first heatsink may be coupled to a heat source such as a processor that may be coupled with a PCB. Also, the movable heatsink may allow access to components, such as dual in-line memory modules (DIMMs) that are next to the first heatsink and under the movable second heatsink. Other embodiments may be described and/or claimed.