公开(公告)号：US20240176084A1

公开(公告)日：2024-05-30

申请号：US18059923

申请日：2022-11-29

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Srinivas V. Pietambaram ,  Brandon Christian Marin ,  Gang Duan ,  Bai Nie

IPC: G02B6/42

CPC classification number: G02B6/428 ,  G02B6/136

Abstract: A PIC first patch architecture includes a solderless electrical connection at a die interconnect surface. Redistribution layers (RDLs) are patterned onto a face of an integrated circuit (IC) die and photonic integrated circuit (PIC) die prior to placement of the RDLs into a cavity in a glass layer. Optical interconnections for the PIC die are protected during RDL patterning and optical waveguides may be patterned into the glass layer fore or after assembling the PIC first patch including the RDL and glass layer.

公开(公告)号：US20240113075A1

公开(公告)日：2024-04-04

申请号：US17956363

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon Marin ,  Srinivas Pietambaram ,  Gang Duan ,  Suddhasattwa Nad

IPC: H01L25/065 ,  H01L21/52 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L21/52 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389

Abstract: Multi-die packages including a glass substrate within a space between adjacent IC dies. Two or more IC die may be placed within recesses formed in a glass substrate. The IC die and glass substrate, along with any conductive vias extending through the glass substrate may be planarized. Organic package dielectric material may then be built up on both sides of the IC dies and glass substrate. Metallization features formed within package dielectric material built up on a first side of the IC die may electrically interconnect the IC dies to package interconnect interfaces that may be further coupled to a host with solder interconnects. Metallization features formed within package dielectric material built up on a second side of the first and second IC dies may electrically interconnect the first IC die to the second IC die.

公开(公告)号：US20240113006A1

公开(公告)日：2024-04-04

申请号：US17937519

申请日：2022-10-03

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Gang Duan ,  Jeremy Ecton ,  Suddhasattwa Nad ,  Srinivas V. Pietambaram

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/14 ,  H01L23/538 ,  H01L23/66 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/145 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5381 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/66 ,  H01L24/16 ,  H01L25/0655 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2924/3841

Abstract: Embodiments of a microelectronic assembly comprise: an interposer structure of glass, a substrate comprising organic dielectric material, the substrate coupled to a first side of the interposer structure; and a plurality of IC dies. A first IC die in the plurality of IC dies is coupled to the substrate by first interconnects, a second IC die in the plurality of IC dies is embedded in the organic dielectric material of the substrate, the second IC die is coupled to the first IC die by second interconnects, the second IC die is coupled to the first side of the interposer structure by third interconnects, and a third IC die in the plurality of IC dies is coupled to a second side of the interposer structure by fourth interconnects, the second side of the interposer structure being opposite the first side of the interposer structure.

公开(公告)号：US20240112971A1

公开(公告)日：2024-04-04

申请号：US17957359

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Yiqun Bai ,  Dingying Xu ,  Srinivas Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Ziyin Lin ,  Bai Nie ,  Haobo Chen ,  Kyle Arrington ,  Bohan Shan

IPC: H01L23/15 ,  H01L21/02 ,  H01L23/495

CPC classification number: H01L23/15 ,  H01L21/02354 ,  H01L23/49506

Abstract: An integrated circuit (IC) device comprises a substrate comprising a glass core. The glass core comprises a first surface and a second surface opposite the first surface, and a first sidewall between the first surface and the second surface. The glass core may include a conductor within a through-glass via extending from the first surface to the second surface and a build-up layer. The glass cord comprises a plurality of first areas of the glass core and a plurality of laser-treated areas on the first sidewall. A first one of the plurality of laser-treated areas may be spaced away from a second one of the plurality of laser-treated areas. A first area may comprise a first nanoporosity and a laser-treated area may comprise a second nanoporosity, wherein the second nanoporosity is greater than the first nanoporosity.

公开(公告)号：US20240112970A1

公开(公告)日：2024-04-04

申请号：US17957355

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Hanyu Song ,  Vinith Bejugam ,  Yonggang Li ,  Gang Duan ,  Aaron Garelick

IPC: H01L23/15 ,  H01L21/48 ,  H01L23/13 ,  H01L23/498

CPC classification number: H01L23/15 ,  H01L21/481 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49822 ,  H01L24/73 ,  H01L2224/73204

Abstract: An integrated circuit (IC) device comprises a substrate comprising a glass core. The glass core includes a first surface, a second surface opposite the first surface, a sidewall between the first surface and the second surface, and a corner region where the first sidewall meets the first surface. A first build-up layer is on at least the first surface. In some embodiments, the corner region comprises a recess and a dielectric material within the recess. In other embodiments, the corner region comprises a first compressive stress and the glass core comprises a second region. The second region comprises a second compressive stress. The first compressive stress is greater than the second compressive stress.

公开(公告)号：US20240105625A1

公开(公告)日：2024-03-28

申请号：US17953511

申请日：2022-09-27

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Kristof Darmawikarta ,  Benjamin Duong ,  Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5386 ,  H01L25/0655 ,  H01L24/17

Abstract: Disclosed herein are microelectronics package architectures utilizing open cavity interconnects for multi-die interconnect bridges and methods of manufacturing the same. The microelectronics packages may include a substrate, a first die, a solder resist layer, a first pad, and a bridge. The substrate may have a substrate surface. The solder resist layer may be connected to the substrate and may define an opening. The first pad may protrude from the substrate surface. The bridge may be located at least partially within the opening and in between the first die and the substrate. The bridge may include a first via that forms a first electrical pathway from the first pad to the first die.

公开(公告)号：US20240079337A1

公开(公告)日：2024-03-07

申请号：US17929471

申请日：2022-09-02

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Tchefor Ndukum ,  Kristof Kuwawi Darmawikarta ,  Sheng Li ,  Srinivas V. Pietambaram ,  Gang Duan ,  Suddhasattwa Nad ,  Jeremy Ecton

IPC: H01L23/538 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/5383 ,  H01L23/49866 ,  H01L23/5381 ,  H01L23/5386 ,  H01L25/0655 ,  H01L24/16

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a conductive pad having a first surface, an opposing second surface, and lateral surfaces extending between the first and second surfaces; a conductive via coupled to the first surface of the conductive pad; a liner on the second surface and on the lateral surfaces of the conductive pad, wherein a material of the liner includes nickel, palladium, or gold; a microelectronic component having a conductive contact; and an interconnect electrically coupling the conductive contact of the microelectronic component and the liner on the second surface of the conductive pad, wherein a material of the interconnect includes nickel or tin.

公开(公告)号：US20240030204A1

公开(公告)日：2024-01-25

申请号：US17871413

申请日：2022-07-22

Applicant: Intel Corporation

Inventor： Gang Duan ,  Hamid R. Azimi ,  Rahul Manepalli ,  Srinivas V. Pietambaram

IPC: H01L25/16 ,  H01L23/427 ,  H01L23/538 ,  G02B6/12

CPC classification number: H01L25/167 ,  H01L23/427 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  G02B6/12004

Abstract: Panel-level high performance computing (HPC) computing architectures and methods for making the same are disclosed. Panel architectures with and without glass cores comprise dielectric layers with interconnect structures (vias, conductive traces) to translate die-level pinouts arranged at a fine pitch to panel-level pinouts arranged at a coarser pitch. Local interconnects and local interconnect components provide for electrical communication between integrated circuit dies in a panel. Coreless panel architectures can comprise a glass reinforcement layer to provide additional mechanical stiffness. The glass reinforcement layer can have interconnect structures and a local interconnect component. Panel embodiments with a glass core or glass reinforcement layer can comprise waveguides and channel a liquid coolant therethrough, and can further comprise photonic integrated circuits. Panel-level manufacturing techniques can enable panels having dimensions larger (e.g., greater than 300 mm) than components fabricated using wafer-level manufacturing techniques.

公开(公告)号：US20240006291A1

公开(公告)日：2024-01-04

申请号：US17855961

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Jeremy D. Ecton ,  Brandon C. Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Jason Steill ,  Yi Yang ,  Marcel Arlan Wall

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/481 ,  H01L21/4853 ,  H01L23/49894 ,  H01L23/49816

Abstract: A substrate package comprises a substrate comprised of buildup layers. The substrate package can further include a passivating layer connected to the substrate and including a pocketed region. The pocketed region can include a first portion thinner than a second portion extending from the first portion. The substrate package can further include a solder ball encapsulated within the pocketed region. Other systems, apparatuses and methods are described.

公开(公告)号：US11780210B2

公开(公告)日：2023-10-10

申请号：US16574252

申请日：2019-09-18

Applicant: Intel Corporation

Inventor： Jieying Kong ,  Gang Duan ,  Srinivas Pietambaram ,  Patrick Quach ,  Dilan Seneviratne

IPC: H01L21/00 ,  B32B17/10 ,  B32B15/20 ,  H01L23/00 ,  H01L23/48

CPC classification number: B32B17/10192 ,  B32B15/20 ,  H01L23/481 ,  H01L24/09 ,  H01L2224/02379

Abstract: Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to a manufacturing process flow for packages that include one or more glass layers that include patterning features, such as electrically conductive traces, RDLs, and vias within the packages. In embodiments, a package may include a glass layer with a first side and a second side opposite the first side, where the glass layer is a dielectric layer. The package may include another layer coupled with the first side of the glass layer, and a pattern on the second side of the glass layer to receive a deposited material in at least a portion of the pattern.