公开(公告)号：US20230320057A1

公开(公告)日：2023-10-05

申请号：US17711875

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Clifford Ong ,  Leonard Guler ,  Mohit Haran ,  Smita Shridharan ,  Reken Patel ,  Charles Wallace ,  Chanaka Munasinghe ,  Pratik Patel

IPC: H01L27/11 ,  H01L27/02 ,  G11C11/412 ,  H01L21/768 ,  H01L23/522 ,  H01L29/423

CPC classification number: H01L27/1104 ,  H01L27/0207 ,  G11C11/412 ,  H01L21/76877 ,  H01L23/5226 ,  H01L29/42392

Abstract: Integrated circuit (IC) devices include transistors with gate, source and drain contact metallization, some of which are jumpered together by a metallization that is recessed below a height of other metallization that is not jumpered. The jumper metallization may provide a local interconnect between terminals of one transistor or adjacent transistors, for example between a gate of one transistor and a source/drain of another transistor. The jumper metallization may not induce the same pitch constraints faced by interconnect line metallization levels employed for more general interconnection. In some examples, a static random-access memory (SRAM) bit-cell includes a jumper metallization joining two transistors of the cell to reduce cell height for a given feature patterning capability.

公开(公告)号：US20230209797A1

公开(公告)日：2023-06-29

申请号：US17560779

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Clifford Ong ,  Leonard Guler ,  Smita Shridharan ,  Zheng Guo ,  Eric Karl ,  Tahir Ghani

IPC: H01L27/11

CPC classification number: H01L27/1108

Abstract: Integrated circuit (IC) static random-access memory (SRAM) comprising colinear pass-gate transistors and pull-down transistors having different nanoribbon widths. A narrower ribbon width within the pass-gate transistor, relative to the pull-down transistor, may reduce read instability of a bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, a transition between narrower and width ribbon widths is symmetrical about a centerline shared by ribbons of both the access and pull-down transistors. In some examples, the ribbon width transition is positioned within an impurity-doped semiconductor region shared by the access and pull-down transistors and may be located under a terminal contact metallization. In some examples, the impurity-doped semiconductor regions surrounding the ribbons of differing width also have differing widths.

公开(公告)号：US11569231B2

公开(公告)日：2023-01-31

申请号：US16354669

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Stephen D Snyder ,  Leonard Guler ,  Richard Schenker ,  Michael K Harper ,  Sam Sivakumar ,  Urusa Alaan ,  Stephanie A Bojarski ,  Achala Bhuwalka

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/16 ,  H01L29/20 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8252 ,  H01L21/8238

Abstract: Techniques are disclosed for non-planar transistors having varying channel widths (Wsi). In some instances, the resulting structure has a fin (or nanowires, nanoribbons, or nanosheets) comprising a first channel region and a second channel region, with a source or drain region between the first channel region and the second channel region. The widths of the respective channel regions are independent of each other, e.g., a first width of the first channel region is different from a second width of the second channel region. The variation in width of a given fin structure may vary in a symmetric fashion or an asymmetric fashion. In an embodiment, a spacer-based forming approach is utilized that allows for abrupt changes in width along a given fin. Sub-resolution fin dimensions are achievable as well.

公开(公告)号：US11189614B2

公开(公告)日：2021-11-30

申请号：US15923885

申请日：2018-03-16

Applicant: INTEL CORPORATION

Inventor： Leonard Guler ,  Elliot Tan

IPC: H01L27/088 ,  H01L27/02 ,  H01L29/10 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/66 ,  H01L21/762 ,  H01L21/306 ,  H01L21/308

Abstract: A grating structure has a plurality of grating members that extend upward from a base in a spaced-apart parallel relationship and include an end member. For example, the grating structure is a plurality of semiconductor fins on a base. The base can be any structure underlying the grating members. The grating members have a member width and a member height. Adjacent grating members are spaced by a grating spacing. A process artifact is adjacent the end member and is spaced from the end member by a horizontal distance consistent with the member spacing. In some cases, the process artifact can be a stub of a second material on or otherwise extending from the base adjacent an end member of the grating structure. In other cases, the process artifact can be a recess in or otherwise extending into the base adjacent an end member of the grating structure.

公开(公告)号：US20200295002A1

公开(公告)日：2020-09-17

申请号：US16354669

申请日：2019-03-15

Applicant: Intel Corporation

Inventor： Stephen D. Snyder ,  Leonard Guler ,  Richard Schenker ,  Michael K. Harper ,  Sam Sivakumar ,  Urusa Alaan ,  Stephanie A. Bojarski ,  Achala Bhuwalka

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/16 ,  H01L29/20 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8252 ,  H01L21/8238

Abstract: Techniques are disclosed for non-planar transistors having varying channel widths (Wsi). In some instances, the resulting structure has a fin (or nanowires, nanoribbons, or nanosheets) comprising a first channel region and a second channel region, with a source or drain region between the first channel region and the second channel region. The widths of the respective channel regions are independent of each other, e.g., a first width of the first channel region is different from a second width of the second channel region. The variation in width of a given fin structure may vary in a symmetric fashion or an asymmetric fashion. In an embodiment, a spacer-based forming approach is utilized that allows for abrupt changes in width along a given fin. Sub-resolution fin dimensions are achievable as well.

公开(公告)号：US20190393351A1

公开(公告)日：2019-12-26

申请号：US16015404

申请日：2018-06-22

Applicant: INTEL CORPORATION

Inventor： Bruce E. Beattie ,  Leonard Guler ,  Biswajeet Guha ,  Jun Sung Kang ,  William Hsu

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant (“low-κ”) material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.