公开(公告)号：US20230420409A1

公开(公告)日：2023-12-28

申请号：US17846086

申请日：2022-06-22

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Omkar G. Karhade ,  Ravindranath Vithal Mahajan ,  Debendra Mallik ,  Nitin A. Deshpande ,  Pushkar Sharad Ranade ,  Wilfred Gomes ,  Abhishek A. Sharma ,  Tahir Ghani ,  Anand S. Murthy ,  Joshua Fryman ,  Stephen Morein ,  Matthew Adiletta ,  Michael Crocker ,  Aaron Gorius

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L25/0652 ,  H01L24/08 ,  H01L23/5226 ,  H01L24/94 ,  H01L2224/80896 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L24/97

Abstract: Embodiments of an integrated circuit (IC) die comprise: a first region having a first surface and a second surface, the first surface being orthogonal to the second surface; and a second region attached to the first region along a planar interface that is orthogonal to the first surface and parallel to the second surface, the second region having a third surface coplanar with the first surface. The first region comprises: a dielectric material; layers of conductive traces in the dielectric material, each layer of the conductive traces being parallel to the second surface such that the conductive traces are orthogonal to the first surface; conductive vias through the dielectric material; and bond-pads on the first surface, the bond-pads comprising portions of the conductive traces exposed on the first surface, and the second region comprises a material different from the dielectric material.

公开(公告)号：US20230299049A1

公开(公告)日：2023-09-21

申请号：US17699028

申请日：2022-03-18

Applicant: Intel Corporation

Inventor： Nitin A. Deshpande ,  Omkar G. Karhade ,  Mohit Bhatia ,  Debendra Mallik

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/16 ,  H01L23/481 ,  H01L24/32 ,  H01L21/76898 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/3128 ,  H01L21/565 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2224/32225 ,  H01L2224/16145 ,  H01L2224/0401

Abstract: A microelectronic component and a method of forming same. The microelectronic component includes: a first substrate having first through vias therein, the first substrate including silicon or glass; a first layer on a front surface of the first substrate and including one or more first dies coupled to the first through vias; a second substrate on a front surface of first layer and having second through vias therein and including silicon or glass; a second layer on a front surface of the second substrate, the first layer between the first substrate and the second substrate, the second layer including one or more second dies coupled to the second through vias; and electrically conductive structures on a back surface of the first substrate coupled to the first through vias.

公开(公告)号：US11735558B2

公开(公告)日：2023-08-22

申请号：US17740501

申请日：2022-05-10

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Mohit Bhatia ,  Anurag Tripathi ,  Takeshi Nakazawa ,  Steve Cho

IPC: H01L23/538 ,  H01L23/00

CPC classification number: H01L24/30 ,  H01L23/5384 ,  H01L24/17 ,  H01L2224/1703

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20230089494A1

公开(公告)日：2023-03-23

申请号：US17482311

申请日：2021-09-22

Applicant: Intel Corporation

Inventor： Xiaoqian Li ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Srinivas V. Pietambaram ,  Mitul Modi

IPC: G02B6/43 ,  G02B6/42

Abstract: Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include a PIC in a first layer having a first surface and an opposing second surface, wherein the first layer includes an insulating material, wherein the PIC has an active side, an opposing backside, and a lateral side substantially perpendicular to the active side and backside, and wherein the PIC is embedded in the insulating material with the active side facing up; an integrated circuit (IC) in a second layer at the second surface of the first layer, wherein the IC is electrically coupled to the active side of the PIC; and an optical component, having a reflector, optically coupled to the lateral side of the PIC and extending at least partially through the insulating material in the first layer along the lateral side of the PIC.

公开(公告)号：US11328937B2

公开(公告)日：2022-05-10

申请号：US16915290

申请日：2020-06-29

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Debendra Mallik ,  Bassam M. Ziadeh ,  Yoshihiro Tomita

IPC: H01L21/00 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L23/16

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

公开(公告)号：US20210391294A1

公开(公告)日：2021-12-16

申请号：US16902887

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Mohit Bhatia ,  Anurag Tripathi ,  Takeshi Nakazawa ,  Steve Cho

IPC: H01L23/00 ,  H01L23/538

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US20210391264A1

公开(公告)日：2021-12-16

申请号：US16902959

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Bai Nie ,  Kristof Kuwawi Darmawikarta ,  Srinivas V. Pietambaram ,  Haobo Chen ,  Gang Duan ,  Jason M. Gamba ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Tarek A. Ibrahim ,  Rahul N. Manepalli ,  Deepak Vasant Kulkarni ,  Ravindra Vijay Tanikella

IPC: H01L23/538 ,  H01L21/48

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US10741419B2

公开(公告)日：2020-08-11

申请号：US16515981

申请日：2019-07-18

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Debendra Mallik ,  Bassam M. Ziadeh ,  Yoshihiro Tomita

IPC: H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/16

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

公开(公告)号：US20190330051A1

公开(公告)日：2019-10-31

申请号：US15962912

申请日：2018-04-25

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande

IPC: B81B7/00 ,  B81C1/00

Abstract: Embodiments include a microelectronic device package structure having a die on a substrate, where a first side of the die is electrically coupled to the substrate, and a second side of the die is covered with a first material having a first thermal conductivity. A second material is adjacent to a sidewall of the die and adjacent to a sidewall of the first material. The second material has second thermal conductivity, smaller than the first thermal conductivity. The second material may have mechanical and/or underfill properties superior to those of the first material. Together, the two materials may provide a package structure having enhanced thermal and mechanical performance.

公开(公告)号：US20180190510A1

公开(公告)日：2018-07-05

申请号：US15899222

申请日：2018-02-19

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nitin A. Deshpande ,  Debendra Mallik ,  Bassam M. Ziadeh ,  Yoshihiro Tomita

IPC: H01L21/56 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L21/563 ,  H01L23/16 ,  H01L23/562 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81007 ,  H01L2224/81011 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81211 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/2064 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/48227

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.