公开(公告)号：US20210005557A1

公开(公告)日：2021-01-07

申请号：US16917947

申请日：2020-07-01

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Thomas Behrens ,  Martin Gruber ,  Thorsten Scharf ,  Peter Strobel

IPC: H01L23/544 ,  H01L23/00

Abstract: A method of mounting electronic components on one or more carrier bodies is disclosed. The method comprises providing a support body with at least one first alignment mark, mounting the one or more carrier bodies, each having at least one second alignment mark, on the support body by alignment between the at least one first alignment mark and the at least one second alignment mark. Thereafter, the method includes mounting the plurality of electronic components on a respective one of the one or more carrier bodies by alignment using the at least one second alignment mark.

公开(公告)号：US20200328141A1

公开(公告)日：2020-10-15

申请号：US16845304

申请日：2020-04-10

Applicant: Infineon Technologies AG

Inventor： Tomasz Naeve ,  Ralf Otremba ,  Thorsten Scharf ,  Markus Dinkel ,  Martin Gruber ,  Elvir Kahrimanovic

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A chip package is provided. The chip package includes a semiconductor chip having on a front side a first connecting pad and a second connecting pad, a carrier having a pad contact area and a recess, encapsulation material encapsulating the conductor chip, a first external connection that is free from or extends out of the encapsulation material, an electrically conductive clip, and a contact structure. The semiconductor chip is arranged with its front side facing the carrier with the first connecting pad over the recess and with the second connecting pad contacting the pad contact area. The clip is arranged over a back side of the semiconductor chip covering the semiconductor chip where it extends over the recess. The electrically conductive contact structure electrically conductively connects the first connecting pad with the first external connection.

公开(公告)号：US20200321309A1

公开(公告)日：2020-10-08

申请号：US16904052

申请日：2020-06-17

Applicant: Infineon Technologies AG

Inventor： Petteri Palm ,  Thorsten Scharf ,  Ralf Wombacher

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/78 ,  H01L23/055 ,  H01L23/48 ,  H01L21/48

Abstract: Electronic module, which comprises a first substrate, a first dielectric layer on the first substrate, at least one electronic chip, which is mounted with a first main surface directly or indirectly on partial region of the first dielectric layer, a second substrate over a second main surface of the at least one electronic chip, and an electrical contacting for the electric contact of the at least one electronic chip through the first dielectric layer, wherein the first adhesion layer on the first substrate extends over an area, which exceeds the first main surface.

公开(公告)号：US20200273781A1

公开(公告)日：2020-08-27

申请号：US16282207

申请日：2019-02-21

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Martin Gruber ,  Josef Hoeglauer ,  Michael Juerss ,  Josef Maerz ,  Thorsten Meyer ,  Bun Kian Tay

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56

Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.

公开(公告)号：US20190333874A1

公开(公告)日：2019-10-31

申请号：US16382866

申请日：2019-04-12

Applicant: Infineon Technologies AG

Inventor： Thomas Bemmerl ,  Martin Gruber ,  Thorsten Scharf

IPC: H01L23/00 ,  H01L23/495 ,  H01L21/48

Abstract: A semiconductor device is disclosed. In one example, the semiconductor device comprises a first semiconductor die comprising a first surface, a second surface opposite to the first surface, and a contact pad disposed on the first surface, a further contact pad spaced apart from the semiconductor die, a clip comprising a first layer of a first metallic material and a second layer of a second metallic material different from the first metallic material, wherein the first layer of the clip is connected with the contact pad, and the second layer of the clip is connected with the further contact pad.

公开(公告)号：US10062671B2

公开(公告)日：2018-08-28

申请号：US15134984

申请日：2016-04-21

Applicant: Infineon Technologies AG

Inventor： Martin Gruber ,  Angela Kessler ,  Thorsten Scharf

IPC: H05K1/18 ,  H01L25/07 ,  H01L23/367 ,  H01L23/498 ,  H01L25/11 ,  H01L25/16

CPC classification number: H01L25/072 ,  H01L23/3672 ,  H01L23/49811 ,  H01L25/115 ,  H01L25/16

Abstract: A semiconductor module includes a circuit board and a power semiconductor chip embedded in the circuit board. The power semiconductor chip has a first load electrode. The semiconductor module further includes a power terminal connector electrically connected to the first load electrode. The embedded power semiconductor chip is positioned laterally within a footprint zone of the power terminal connector.

公开(公告)号：US12211824B2

公开(公告)日：2025-01-28

申请号：US18130952

申请日：2023-04-05

Applicant: Infineon Technologies AG

Inventor： Ivan Nikitin ,  Thorsten Scharf ,  Marco Bäßler ,  Andreas Grassmann ,  Waldemar Jakobi

IPC: H01L25/07 ,  H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A power semiconductor package includes first power semiconductor dies attached to a metallization layer of at least one first power electronics carrier and second power semiconductor dies attached to a metallization layer of at least one second power electronics carrier. A first lead frame includes a first structured metal frame electrically connected to a load terminal of each first power semiconductor die, and a second structured metal frame electrically connected to a load terminal of each second power semiconductor die and to the metallization layer of the first power electronics carrier. A second lead frame above the first lead frame includes first and second leads electrically connected to the metallization layer of the second power electronics carrier, a third lead between the first and second leads and electrically connected to the first structured metal frame, and a fourth lead electrically connected to the second structured metal frame.

公开(公告)号：US12154886B2

公开(公告)日：2024-11-26

申请号：US17502163

申请日：2021-10-15

Applicant: Infineon Technologies AG

Inventor： Thorsten Meyer ,  Martin Gruber ,  Thorsten Scharf

IPC: H01L23/02 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor package is disclosed. In one example, the package includes a non-power chip including a first electrical contact arranged at a first main surface of the non-power chip. The semiconductor package further includes a power chip comprising a second electrical contact arranged at a second main surface of the power chip. A first electrical redistribution layer coupled to the first electrical contact and a second electrical redistribution layer coupled to the second electrical contact. When measured in a first direction vertical to at least one of the first main surface or the second main surface, a maximum thickness of at least a section of the first electrical redistribution layer is smaller than a maximum thickness of the second electrical redistribution layer.

公开(公告)号：US20240355767A1

公开(公告)日：2024-10-24

申请号：US18761675

申请日：2024-07-02

Applicant: Infineon Technologies AG

Inventor： Petteri Palm ,  Thorsten Scharf

IPC: H01L23/00 ,  H01L23/538 ,  H01L25/04 ,  H05K1/18 ,  H05K3/00

CPC classification number: H01L24/06 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/83 ,  H01L25/04 ,  H05K1/188 ,  H05K3/007 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/06182 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2224/8019 ,  H01L2224/83132 ,  H01L2224/83192 ,  H01L2224/83447 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/15747 ,  H05K2203/0152

Abstract: A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

公开(公告)号：US20240332142A1

公开(公告)日：2024-10-03

申请号：US18609586

申请日：2024-03-19

Applicant: Infineon Technologies AG

Inventor： Michael Fügl ,  Thorsten Scharf

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/60 ,  H01L23/31

CPC classification number: H01L23/49555 ,  H01L21/56 ,  H01L21/60 ,  H01L23/3107 ,  H01L23/49575

Abstract: A power semiconductor module includes an encapsulation encapsulating power semiconductor dies. The encapsulation includes lateral sides connecting first and second opposite sides. First and second power contacts are electrically coupled to the power semiconductor dies. An isolation part arranged between the power contacts electrically isolates the contacts from one another. The power contacts have a flat shape and are stacked such that their broadest surfaces at least partially overlap. A first portion of the power contacts is parallel to a first plane. A second portion is twisted and/or bent with respect to the first portion such that the second portion is parallel to a second plane arranged at a non-zero angle with respect to the first plane. At least a part of the first portion is encapsulated by the encapsulation. At least a part of the second portion is exposed from the encapsulation at one of the lateral sides.