公开(公告)号：US20230387068A1

公开(公告)日：2023-11-30

申请号：US18366843

申请日：2023-08-08

Applicant: Infineon Technologies AG

Inventor： Melvin Levardo ,  Ryan Ross Agbay Alinea ,  Markus Dinkel

IPC: H01L23/00

CPC classification number: H01L24/72 ,  H01L24/73

Abstract: A method of manufacturing a package includes: connecting an electronic component with a carrier by a clip having at least one locking recess; partially encapsulating the clip by an encapsulant so that at least part of a main surface of the clip remains partially exposed with respect to the encapsulant; and locking the encapsulant and the clip by accommodating material of the encapsulant in the at least one locking recess.

公开(公告)号：US11342252B2

公开(公告)日：2022-05-24

申请号：US17063927

申请日：2020-10-06

Applicant: Infineon Technologies AG

Inventor： Stefan Macheiner ,  Markus Dinkel

IPC: H01L21/48 ,  H01L23/495 ,  H01L21/288 ,  H01L21/56 ,  H01L21/66 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor device includes a leadframe, a semiconductor die attached to the leadframe, and an encapsulation material encapsulating the semiconductor die and a portion of the leadframe. The leadframe includes a first main face and a second main face opposite to the first main face. The leadframe includes leads wherein each lead includes a fully plated end face extending between an unplated first sidewall and an unplated second sidewall opposite to the first sidewall. The end face and the first and second sidewalls of each lead are perpendicular to the first and second main faces.

公开(公告)号：US20210035876A1

公开(公告)日：2021-02-04

申请号：US16939303

申请日：2020-07-27

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Markus Dinkel ,  Josef Hoeglauer ,  Angela Kessler

IPC: H01L23/31 ,  H01L23/495 ,  H01L25/065

Abstract: A semiconductor package is disclosed. In one example, the semiconductor package includes a package body and a semiconductor component encapsulated in the package body. A cavity is formed in a bottom surface of the package body.

公开(公告)号：US09922904B2

公开(公告)日：2018-03-20

申请号：US14721359

申请日：2015-05-26

Applicant: Infineon Technologies AG

Inventor： Markus Dinkel

IPC: H01L23/495 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/49503 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49551 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/40245 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/8382 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor device includes a planar first lead frame including a die pad, a semiconductor chip coupled to the die pad, and a second lead frame coupled to the first lead frame. The second lead frame includes leads arranged such that the die pad is downset with respect to the leads.

公开(公告)号：US20160013176A1

公开(公告)日：2016-01-14

申请号：US14859928

申请日：2015-09-21

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Vanessa Capodieci ,  Markus Dinkel ,  Uwe Schmalzbauer

IPC: H01L27/02 ,  H01L29/06 ,  G01R31/26 ,  H01L23/58 ,  H01L29/40 ,  H01L21/66 ,  H01L27/088

CPC classification number: H01L27/0207 ,  G01R31/26 ,  H01L22/34 ,  H01L23/13 ,  H01L23/48 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/40 ,  H01L29/407 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate including a main surface with a polygonal geometry and a main electric circuit manufactured within a main region on the semiconductor substrate. The main electric circuit is operable to perform an electric main function. The main region extends over the main surface of the semiconductor substrate leaving open at least one corner area at a corner of the polygonal geometry of the main surface of the semiconductor substrate. The corner area extends at least 300 μm along the edges of the semiconductor substrate beginning at the corner.

Abstract translation: 半导体器件包括半导体衬底，该半导体衬底包括具有多边形几何形状的主表面和在半导体衬底上的主区域内制造的主电路。 主电路可操作以执行电主功能。 主区域在半导体衬底的主表面上延伸，在半导体衬底的主表面的多边形几何形状的拐角处打开至少一个拐角区域。 拐角区域从角部开始沿着半导体衬底的边缘延伸至少300μm。

公开(公告)号：US20140167044A1

公开(公告)日：2014-06-19

申请号：US13752670

申请日：2013-01-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Markus Zundel ,  Vanessa Capodieci ,  Markus Dinkel ,  Uwe Schmalzbauer

IPC: H01L23/48 ,  H01L21/02

CPC classification number: H01L27/0207 ,  G01R31/26 ,  H01L22/34 ,  H01L23/13 ,  H01L23/48 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/40 ,  H01L29/407 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a semiconductor substrate including a main surface with a polygonal geometry and a main electric circuit manufactured within a main region on the semiconductor substrate. The main electric circuit is operable to perform an electric main function. The main region extends over the main surface of the semiconductor substrate leaving open at least one corner area at a corner of the polygonal geometry of the main surface of the semiconductor substrate. The corner area extends at least 300 μm along the edges of the semiconductor substrate beginning at the corner.

Abstract translation: 半导体器件包括半导体衬底，该半导体衬底包括具有多边形几何形状的主表面和在半导体衬底上的主区域内制造的主电路。 主电路可操作以执行电主功能。 主区域在半导体衬底的主表面上延伸，在半导体衬底的主表面的多边形几何形状的拐角处打开至少一个拐角区域。 拐角区域从角部开始沿着半导体衬底的边缘延伸至少300μm。

公开(公告)号：US20230095545A1

公开(公告)日：2023-03-30

申请号：US17950662

申请日：2022-09-22

Applicant: Infineon Technologies AG

Inventor： Paul Armand Calo ,  Thomas Bemmerl ,  Joo Ming Goa ,  Edward Myers ,  Wee Boon Tay ,  Stefan Macheiner ,  Markus Dinkel ,  Andreas Piller

IPC: H01L23/495 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31

Abstract: A semiconductor package includes a leadframe including a diepad and a first row of leads, wherein at least one lead of the first row of leads is physically separated from the diepad by a gap. The semiconductor package further includes a semiconductor component arranged on the leadframe. The semiconductor package further includes an encapsulation material encapsulating the leadframe and the semiconductor component, wherein the encapsulation material includes a bottom surface arranged at a bottom surface of the semiconductor package, a top surface and a side surface extending from the bottom surface to the top surface. A side surface of at least one lead of the first row of leads is flush with the side surface of the encapsulation material. The flush side surface of the at least one lead is covered by an electroplated metal coating.

公开(公告)号：US10796986B2

公开(公告)日：2020-10-06

申请号：US15075266

申请日：2016-03-21

Applicant: Infineon Technologies AG

Inventor： Stefan Macheiner ,  Markus Dinkel

IPC: H01L23/495 ,  H01L21/288 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor device includes a leadframe, a semiconductor die attached to the leadframe, and an encapsulation material encapsulating the semiconductor die and a portion of the leadframe. The leadframe includes a first main face and a second main face opposite to the first main face. The leadframe includes leads wherein each lead includes a fully plated end face extending between an unplated first sidewall and an unplated second sidewall opposite to the first sidewall. The end face and the first and second sidewalls of each lead are perpendicular to the first and second main faces.

公开(公告)号：US20170287820A1

公开(公告)日：2017-10-05

申请号：US15089668

申请日：2016-04-04

Applicant: Infineon Technologies AG

Inventor： Dirk Ahlers ,  Markus Dinkel

IPC: H01L23/495 ,  H02M7/44 ,  H01L21/56 ,  H02M7/00 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/49575 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L2224/0603 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49113 ,  H02M7/003 ,  H02M7/44 ,  H02M7/5387

Abstract: A semiconductor package includes a substrate, a first transistor die secured to the substrate and a second transistor die secured to the substrate. The first transistor die has a source terminal at a bottom side of the first transistor die which faces the substrate and a drain terminal and a gate terminal at a top side of the first transistor die which faces away from the substrate. The second transistor die has a drain terminal at a bottom side of the second transistor die which faces the substrate and a source terminal and a gate terminal at a top side of the second transistor die which faces away from the substrate. The package also includes a common electrical connection between the drain terminal of the first transistor die and the source terminal of the second transistor die.

公开(公告)号：US09681558B2

公开(公告)日：2017-06-13

申请号：US14457663

申请日：2014-08-12

Applicant: Infineon Technologies AG

Inventor： Liu Chen ,  Markus Dinkel ,  Toni Salminen

IPC: H05K7/00 ,  H05K3/40 ,  H05K7/06 ,  H05K3/46 ,  H05K3/00

CPC classification number: H05K3/40 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/18 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/19105 ,  H05K3/0017 ,  H05K3/4697 ,  H05K7/06 ,  H05K2201/10166

Abstract: A integrated power module with integrated power electronic circuitry and logic circuitry includes an embedded power semiconductor module including one or more power semiconductor dies embedded in a dielectric material, a multi-layer logic printed circuit board with one or more logic dies mounted to a surface of the logic printed circuit board, and a flexible connection integrally formed between the embedded power semiconductor module and the logic printed circuit board. The flexible connection mechanically connects the embedded power semiconductor module to the logic printed circuit board and provides an electrical pathway between the embedded power semiconductor module and the logic printed circuit board. A method of manufacturing the integrated power module is also provided.