公开(公告)号：US20230369181A1

公开(公告)日：2023-11-16

申请号：US17743601

申请日：2022-05-13

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Frank Singer

IPC: H01L23/495 ,  H01L23/31

CPC classification number: H01L23/49534 ,  H01L23/49503 ,  H01L23/3142

Abstract: A method of forming a semiconductor package includes providing a first metal substrate; and mounting a stacked arrangement on the first metal substrate, the stacked arrangement comprising a semiconductor die, wherein mounting the stacked arrangement includes: providing a first layer of attachment material between the first metal substrate and the stacked arrangement; and providing a second layer of attachment material within the stacked arrangement at an interface with the semiconductor die, wherein at least one of the first and second layers of attachment material is a compressible layer that includes one or more elastomeric elements embedded within a matrix of solder material.

公开(公告)号：US20230051100A1

公开(公告)日：2023-02-16

申请号：US17980004

申请日：2022-11-03

Applicant: Infineon Technologies AG

Inventor： Bun Kian Tay ,  Mei Yih Goh ,  Martin Gruber ,  Josef Hoeglauer ,  Michael Juerss ,  Josef Maerz ,  Thorsten Meyer ,  Thorsten Scharf ,  Chee Voon Tan

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L23/495 ,  H01L21/48

Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.

公开(公告)号：US11309277B2

公开(公告)日：2022-04-19

申请号：US16904052

申请日：2020-06-17

Applicant: Infineon Technologies AG

Inventor： Petteri Palm ,  Thorsten Scharf ,  Ralf Wombacher

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/78 ,  H01L23/055 ,  H01L23/48 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498

Abstract: Electronic module, which comprises a first substrate, a first dielectric layer on the first substrate, at least one electronic chip, which is mounted with a first main surface directly or indirectly on partial region of the first dielectric layer, a second substrate over a second main surface of the at least one electronic chip, and an electrical contacting for the electric contact of the at least one electronic chip through the first dielectric layer, wherein the first adhesion layer on the first substrate extends over an area, which exceeds the first main surface.

公开(公告)号：US20210151401A1

公开(公告)日：2021-05-20

申请号：US17158226

申请日：2021-01-26

Applicant: Infineon Technologies AG

Inventor： Petteri Palm ,  Thorsten Scharf

IPC: H01L23/00 ,  H01L23/538 ,  H05K3/00 ,  H05K1/18 ,  H01L25/04

Abstract: A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

公开(公告)号：US11004700B2

公开(公告)日：2021-05-11

申请号：US16546913

申请日：2019-08-21

Applicant: Infineon Technologies AG

Inventor： Richard Knipper ,  Thorsten Scharf

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L21/027

Abstract: A method includes: providing a semiconductor die having a first main surface, a second main surface opposite the first main surface, and an edge between the first main surface and the second main surface; applying a temporary spacer to a first part of the first main surface of the semiconductor die, the first part being positioned inward from a peripheral part of the first main surface; after applying the temporary spacer, embedding the semiconductor die at least partly in an embedding material, the embedding material covering the edge and the peripheral part of the first main surface of the semiconductor die and contacting a sidewall of the temporary spacer; and after the embedding, removing the temporary spacer from the first main surface of the semiconductor die to expose the first part of the first main surface of the semiconductor die. A semiconductor device produced by the method is also provided.

公开(公告)号：US10903180B2

公开(公告)日：2021-01-26

申请号：US15949632

申请日：2018-04-10

Applicant: Infineon Technologies AG

Inventor： Petteri Palm ,  Thorsten Scharf

IPC: H01L23/00 ,  H01L23/538 ,  H05K3/00 ,  H05K1/18 ,  H01L25/04

Abstract: A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

公开(公告)号：US20200227312A1

公开(公告)日：2020-07-16

申请号：US16690984

申请日：2019-11-21

Applicant: Infineon Technologies AG

Inventor： Irmgard Escher-Poeppel ,  Thorsten Scharf ,  Catharina Wille

IPC: H01L21/768 ,  H01L23/16 ,  H01L23/31 ,  H01L23/48

Abstract: A semiconductor device and method is disclosed. In one example, the method includes forming a recess in an electrically insulating encapsulation material, wherein the encapsulation material at least partly encapsulates a semiconductor chip. The method further includes forming an adhesion promoting structure in the recess. The method further includes spraying an electrically conductive material into the recess, wherein the adhesion promoting structure is configured to provide an adhesion between the sprayed electrically conductive material and the encapsulation material.

公开(公告)号：US20200006187A1

公开(公告)日：2020-01-02

申请号：US16452777

申请日：2019-06-26

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Irmgard Escher-Poeppel ,  Martin Gruber ,  Michael Juerss ,  Thorsten Scharf

IPC: H01L23/367 ,  H01L23/495 ,  H01L23/532 ,  H01L23/373 ,  H01L23/31

Abstract: A heat dissipation device includes a first part having a first material and a surface portion, and a second part on the surface portion. The second part has a second material and a porosity.

公开(公告)号：US20190304858A1

公开(公告)日：2019-10-03

申请号：US16365837

申请日：2019-03-27

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Ralf Otremba ,  Thomas Bemmerl ,  Irmgard Escher-Poeppel ,  Martin Gruber ,  Michael Juerss ,  Thorsten Meyer ,  Xaver Schloegel

IPC: H01L23/053 ,  H01L23/40 ,  H01L23/00 ,  H01L23/08

Abstract: A semiconductor package system comprises a semiconductor package and a cap. The semiconductor package comprises a die pad, a chip mounted or arranged to a first main face of the die pad and an encapsulation body encapsulating the chip and the die pad. The cap covers at least partly an exposed second main face of the die pad. The cap comprises a cap body of an electrically insulating and thermally conductive material and a fastening system fastening the cap to the semiconductor package. The fastening system extends from the cap body towards the encapsulation body or along a side surface of the semiconductor package.

公开(公告)号：US10229891B2

公开(公告)日：2019-03-12

申请号：US15436778

申请日：2017-02-18

Applicant: Infineon Technologies AG

Inventor： Thorsten Scharf ,  Steffen Jordan ,  Wolfgang Schober ,  Thomas Ziegler

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/538 ,  H01L23/498

Abstract: A package comprising an electronic chip, a laminate-type encapsulant at least partially encapsulating the electronic chip, a wiring structure extending from the electronic chip up to a contact pad, and a completely galvanically formed solderable exterior electric contact electrically coupled with the electronic chip by being arranged on the contact pad.