公开(公告)号：US10296333B2

公开(公告)日：2019-05-21

申请号：US15391695

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Asaf Rubinstein ,  Tom Aviram

IPC: G06F9/30 ,  G06F9/38 ,  G06F15/80

Abstract: Vector single instruction multiple data (SIMD) shift and rotate instructions are provided specifying: a destination vector register comprising fields to store vector elements, a first vector register, a vector element size, and a second vector register. Vector data fields of a first element size are duplicated. Duplicate vector data fields are stored as corresponding data fields of twice the first element size. Control logic receives an element size for performing a SIMD shift or rotation operation. Through selectors corresponding to a vector element, portions are selected from the duplicated data fields, the selectors corresponding to any particular vector element select all portions similarly from the duplicated data fields for that particular vector element responsive to the first element size, but selectors corresponding to any particular vector element select at least two portions from the duplicated data fields differently for that particular vector element responsive to a second element size.

公开(公告)号：US20190050346A1

公开(公告)日：2019-02-14

申请号：US15920145

申请日：2018-03-13

Applicant: INTEL CORPORATION

Inventor： Zvika Greenfield ,  Eshel Serlin ,  Asaf Rubinstein ,  Eli Abadi

IPC: G06F12/123

Abstract: Embodiments of the present disclosure are directed towards a computing device having a cache memory device with a scrubber logic. In some embodiments, the scrubber logic controller may be coupled with the cache device, and may perform a selection for eviction from the cache device a portion of data stored in the cache device, based at least in part on one or more selection criteria, at a dynamically adjusted level of aggressiveness of the selection performance. The scrubber logic controller may adjust the level of aggressiveness of the selection performance, based at least in part on a determined time left to complete the selection performance at a current level of aggressiveness. Other embodiments may be described and/or claimed.

公开(公告)号：US10055360B2

公开(公告)日：2018-08-21

申请号：US14975752

申请日：2015-12-19

Applicant: Intel Corporation

Inventor： Daniel Greenspan ,  Blaise Fanning ,  Yoav Lossin ,  Asaf Rubinstein

IPC: G06F12/00 ,  G06F12/123 ,  G06F12/0891 ,  G06F12/0897

CPC classification number: G06F12/123 ,  G06F12/0891 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/60 ,  Y02D10/13

Abstract: A method and apparatus are described for a shared LRU policy between cache levels. For example, one embodiment of the invention comprises: a level N cache to store a first plurality of entries; a level N+1 cache to store a second plurality of entries; the level N+1 cache to initially be provided with responsibility for implementing a least recently used (LRU) eviction policy for a first entry until receipt of a request for the first entry from the level N cache at which time the entry is copied from the level N+1 cache to the level N cache, the level N cache to then be provided with responsibility for implementing the LRU policy until the first entry is evicted from the level N cache, wherein upon being notified that the first entry has been evicted from the level N cache, the level N+1 cache to resume responsibility for implementing the LRU eviction policy with respect to the first entry.

公开(公告)号：US20180089096A1

公开(公告)日：2018-03-29

申请号：US15276856

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Daniel Greenspan ,  Randy Osborne ,  Zvika Greenfield ,  Israel Diamand ,  Asaf Rubinstein

IPC: G06F12/0893 ,  G09G5/39

CPC classification number: G09G5/39 ,  G06F3/14 ,  G06F12/0895 ,  G06F2212/604 ,  G09G5/393 ,  G09G2360/121

Abstract: An electronic processing system may include a processor and a multi-level memory coupled to the processor, the multi-level memory including at least a main memory and a fast memory, the fast memory having relatively faster performance as compared to the main memory. The system may further include a fast memory controller coupled to the fast memory and a graphics controller coupled to the fast memory controller. The fast memory may include a cache portion allocated to a cache region to allow a corresponding mapping of elements of the main memory in the cache region, and a graphics portion allocated to a graphics region for the graphics controller with no corresponding mapping of the graphics region with the main memory.

公开(公告)号：US20180046579A1

公开(公告)日：2018-02-15

申请号：US15794172

申请日：2017-10-26

Applicant: Intel Corporation

Inventor： Daniel Greenspan ,  Anant V. Nori ,  Supratik Majumder ,  Yoav Lossin ,  Asaf Rubinstein

IPC: G06F12/0864 ,  G06F12/0846 ,  G06F12/128 ,  G06F12/123

CPC classification number: G06F12/0864 ,  G06F12/0851 ,  G06F12/123 ,  G06F12/128 ,  G06F2212/1024 ,  G06F2212/6032 ,  Y02D10/13

Abstract: A cache controller is to allocate memory within set-associative cache that includes a plurality of sets of ways. The cache controller is to request to assign an entry for a system address in the set-associative cache and execute a function to determine a set, from a series of sets within the plurality of sets of ways, to which to allocate the entry in the set-associative cache. The cache controller is further to identify an available number of ways in the set and identify a way that is available in response to execution of a way bias algorithm. The cache controller is also to determine whether the way is among the ways available within the set and select the way for allocation of the entry in response to the way being among the ways available within the set.