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公开(公告)号：US09268393B2
公开(公告)日：2016-02-23
申请号：US13997295
申请日：2012-11-30
Applicant: Intel Corporation
Inventor： Ankush Varma , Krishnakanth Sistla , Martin T. Rowland , Brian J. Griffith , Viktor D. Vogman , Joseph R. Doucette , Eric J. Dehaemer , Vivek Garg , Chris Poirier , Jeremy J. Shrall , Avinash N. Ananthakrishnan , Stephen H. Gunther
CPC classification number: G06F1/3234 , G06F1/06 , G06F1/324 , G06F8/4432 , Y02D10/126
Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently perform graphics operations; and, a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，处理器包括多个核心，每个核心各自独立地执行指令，多个图形引擎各自独立地执行图形操作; 以及功率控制单元，其耦合到所述多个核以控制所述处理器的功率消耗，其中所述功率控制单元包括功率偏移控制逻辑，以将所述处理器的功率消耗水平限制在高于限定功率极限以上 工作周期的占空比部分。 描述和要求保护其他实施例。
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公开(公告)号：US09189046B2
公开(公告)日：2015-11-17
申请号：US13783978
申请日：2013-03-04
Applicant: Intel Corporation
Inventor： Xiuting C. Man , Michael N. Derr , Jay D. Schwartz , Stephen H. Gunther , Jeremy J. Shrall , Shaun M. Conrad , Avinash N. Ananthakrishnan
CPC classification number: G06F1/32 , G06F1/206 , G06F1/3206 , G06F1/324 , Y02D10/126
Abstract: In an embodiment, a processor includes a first domain with at least one core to execute instructions and a second domain coupled to the first domain and including at least one non-core circuit. These domains can operate at independent frequencies, and a power control unit coupled to the domains may include a thermal logic to cause a reduction in a frequency of the first domain responsive to occurrence of a thermal event in the second domain. Other embodiments are described and claimed.
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23.发明授权公开(公告)号：US09176565B2
公开(公告)日：2015-11-03
申请号：US13782578
申请日：2013-03-01
Applicant: Intel Corporation
Inventor： Avinash N. Ananthakrishnan , Efraim Rotem , Doron Rajwan , Jeremy J. Shrall , Eric C. Samson , Eliezer Weissmann , Ryan Wells
CPC classification number: G06F1/324 , G06F1/26 , G06F1/30 , G06F1/3203 , G06F1/3234 , G06F1/3243 , G06F13/14 , Y02D10/126
Abstract: In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括一种用于确定多域处理器的非核心域不以非核域所请求的频率操作的方法，将来自非核心域的请求发送到功率 控制器降低多域处理器核心域的频率，并响应请求，降低核心域频率。 描述和要求保护其他实施例。
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公开(公告)号：US09170624B2
公开(公告)日：2015-10-27
申请号：US13782473
申请日：2013-03-01
Applicant: Intel Corporation
Inventor： Krishnakanth V. Sistla , Jeremy Shrall , Stephen H. Gunther , Efraim Rotem , Alon Naveh , Eliezer Weissmann , Anil Aggarwal , Martin T. Rowland , Ankush Varma , Ian M. Steiner , Matthew Bace , Avinash N. Ananthakrishnan , Jason Brandt
CPC classification number: G06F1/3275 , G06F1/266 , G06F1/3203 , G06F1/3206 , G06F1/3234
Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.
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公开(公告)号：US12210395B2
公开(公告)日：2025-01-28
申请号：US18474377
申请日：2023-09-26
Applicant: Intel Corporation
IPC: G06F1/26 , G06F1/32 , G06F1/3203 , G06F1/3234 , G06F1/3287 , G06F1/3296 , G06F9/46 , G06F13/42 , G06F30/00
Abstract: In one embodiment, a processor includes: a plurality of cores; a first storage to store parameter information for a voltage regulator to couple to the processor via a voltage regulator interface; and a power controller to control power consumption of the processor. The power controller may determine a performance state for one or more cores of the processor and include a hardware logic to generate a message for the voltage regulator based at least in part on the parameter information, where this message is to cause the voltage regulator to output a voltage to enable the one or more cores to operate at the performance state. Other embodiments are described and claimed.
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Patent Agency Ranking
公开(公告)号：US11782492B2
公开(公告)日：2023-10-10
申请号：US17828471
申请日：2022-05-31
Applicant: Intel Corporation
IPC: G06F1/3296 , G06F1/26 , G06F1/3287 , G06F13/42 , G06F1/32 , G06F1/3203 , G06F9/46 , G06F1/3234 , G06F30/00
CPC classification number: G06F1/266 , G06F1/26 , G06F1/32 , G06F1/3203 , G06F1/3243 , G06F1/3287 , G06F1/3296 , G06F9/46 , G06F13/4282 , G06F30/00 , G06F2213/0016 , Y02B70/10 , Y02D10/00
Abstract: In one embodiment, a processor includes: a plurality of cores; a first storage to store parameter information for a voltage regulator to couple to the processor via a voltage regulator interface; and a power controller to control power consumption of the processor. The power controller may determine a performance state for one or more cores of the processor and include a hardware logic to generate a message for the voltage regulator based at least in part on the parameter information, where this message is to cause the voltage regulator to output a voltage to enable the one or more cores to operate at the performance state. Other embodiments are described and claimed.
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公开(公告)号：US10761580B2
公开(公告)日：2020-09-01
申请号：US16227103
申请日：2018-12-20
Applicant: Intel Corporation
IPC: G06F1/32 , G06F1/26 , G06F1/3287 , G06F13/42 , G06F1/3203 , G06F1/3296 , G06F9/46 , G06F1/3234 , G06F30/00
Abstract: In one embodiment, a processor includes: a plurality of cores; a first storage to store parameter information for a voltage regulator to couple to the processor via a voltage regulator interface; and a power controller to control power consumption of the processor. The power controller may determine a performance state for one or more cores of the processor and include a hardware logic to generate a message for the voltage regulator based at least in part on the parameter information, where this message is to cause the voltage regulator to output a voltage to enable the one or more cores to operate at the performance state. Other embodiments are described and claimed.
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公开(公告)号：US10705588B2
公开(公告)日：2020-07-07
申请号：US16249103
申请日：2019-01-16
Applicant: Intel Corporation
Inventor： Avinash N. Ananthakrishnan , Inder M. Sodhi , Efraim Rotem , Doron Rajwan , Eliezer Weissmann , Ryan Wells
IPC: G06F1/324 , G06F1/3293 , G06F1/3203 , G11C7/22 , G06F13/42 , G06F1/3296 , G06F13/40
Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.
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公开(公告)号：US10423206B2
公开(公告)日：2019-09-24
申请号：US15252529
申请日：2016-08-31
Applicant: Intel Corporation
Inventor： Avinash N. Ananthakrishnan , Jeremy J. Shrall , Anupama Suryanarayanan , Ameya Ambardekar , Craig Topper , Eric R. Heit , Joseph M. Alberts
IPC: G06F9/00 , G06F1/28 , G06F12/0897 , G06F12/0875 , G06F12/084 , G06F1/30 , G06F1/3296
Abstract: In one embodiment, a processor includes a plurality of cores and a power controller. This power controller in turn may include a voltage ramp logic to pre-empt a voltage ramp of a voltage regulator from a first voltage to a second voltage, responsive to a request for a second core to exit a low power state. Other embodiments are described and claimed.
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30.发明授权公开(公告)号：US10379904B2
公开(公告)日：2019-08-13
申请号：US15252511
申请日：2016-08-31
Applicant: Intel Corporation
Inventor： Eliezer Weissmann , Israel Hirsh , Efraim Rotem , Doron Rajwan , Avinash N. Ananthakrishnan , Natanel Abitan , Ido Melamed , Guy M. Therien
Abstract: In one embodiment, a processor includes: a first storage to store a set of common performance state request settings; a second storage to store a set of thread performance state request settings; and a controller to control a performance state of a first core based on a combination of at least one of the set of common performance state request settings and at least one of the set of thread performance state request settings. Other embodiments are described and claimed.
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