公开(公告)号：US20170352406A1

公开(公告)日：2017-12-07

申请号：US15174946

申请日：2016-06-06

Applicant: Intel Corporation

Inventor： Bruce QUERBACH ,  Kuljit S. BAINS ,  John B. HALBERT

IPC: G11C11/406 ,  G06F3/06 ,  G11C14/00

CPC classification number: G11C11/40618 ,  G06F3/0604 ,  G06F3/0632 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/40622 ,  G11C14/0009

Abstract: A memory subsystem enables a refresh abort command. A memory controller can issue an abort for an in-process refresh command sent to a memory device. The refresh abort enables the memory controller to more precisely control the timing of operations executed by memory devices in the case where a refresh command causes refresh of multiple rows of memory. The memory controller can issue a refresh command during active operation of the memory device, which is active operation refresh as opposed to self-refresh when the memory device controls refreshing. The memory controller can then issue a refresh abort during the refresh, and prior to completion of the refresh. The memory controller thus has deterministic control over both the start of refresh as well as when the memory device can be made available for access.

公开(公告)号：US20170237431A1

公开(公告)日：2017-08-17

申请号：US15423431

申请日：2017-02-02

Applicant: Intel Corporation

Inventor： James A. McCALL ,  Kuljit S. BAINS

IPC: H03K19/00 ,  G11C11/4074 ,  G11C11/4093

CPC classification number: H03K19/0005 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C11/4074 ,  G11C11/4093

Abstract: Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory; assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level.

公开(公告)号：US20150317096A1

公开(公告)日：2015-11-05

申请号：US14440064

申请日：2013-11-22

Applicant: Kuljit S. BAINS ,  INTEL CORPORATION

Inventor： Kuljit S. BAINS

IPC: G06F3/06

CPC classification number: G11C11/4074 ,  G06F3/0604 ,  G06F3/0637 ,  G06F3/0673 ,  G06F13/1663 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1084 ,  G11C7/109 ,  G11C8/06 ,  G11C11/408 ,  Y10T29/41

Abstract: Techniques and mechanisms for determining a timing of a command to access a memory device resource. In an embodiment, a multi-cycle command which is exchanged from a memory controller to a memory device, wherein the multi-cycle command indicates an access to a bank of the memory device. Timing of the one or more other commands is controlled, based on the multi-cycle command, to enforce a time delay parameter which describes an operational constraint of the memory device. In another embodiment, timing of one or more commands is determined with reference to a beginning of a last cycle of a multi-cycle command.

Abstract translation: 用于确定访问存储器设备资源的命令的定时的技术和机制。 在一个实施例中，从存储器控制器交换到存储器件的多循环命令，其中多周期命令指示对存储器件的存储体的访问。 基于多周期命令来控制一个或多个其他命令的定时，以强制描述存储器件的操作约束的时间延迟参数。 在另一个实施例中，参考多周期命令的最后一个周期的开始来确定一个或多个命令的定时。

公开(公告)号：US20150309726A1

公开(公告)日：2015-10-29

申请号：US14440066

申请日：2013-11-22

Applicant: James A. MCCALL ,  Kuljit S. BAINS ,  Intel Corporation

Inventor： James A. MCCALL ,  Kuljit S. BAINS

IPC: G06F3/06 ,  G11C5/14

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0673 ,  G11C5/147 ,  G11C7/1057 ,  G11C7/1084 ,  G11C29/021 ,  G11C29/028

Abstract: Techniques and mechanisms for a memory device to concurrently receive and process signals each based on a different respective reference voltage level. In an embodiment, an input/output (I/O) interface of a memory device includes receiver circuits each to process a respective signal received via a corresponding signal line of a bus. In response to one or more configuration commands, a first receiver circuit is configured to process a first signal based on a first reference voltage level and a second receiver circuit is configured to process a second signal based on a second reference voltage level. In another embodiment, a memory controller sends the one or more configuration commands to such a memory device based on an evaluation of voltage swing characteristics each corresponding to a different respective signal line of a bus.

Abstract translation: 用于存储器件的技术和机制，用于基于不同的相应参考电压电平同时接收和处理信号。 在一个实施例中，存储器件的输入/输出（I / O）接口包括接收器电路，每个接收器电路用于处理经由总线的相应信号线接收到的相应信号。 响应于一个或多个配置命令，第一接收器电路被配置为基于第一参考电压电平处理第一信号，并且第二接收器电路被配置为基于第二参考电压电平来处理第二信号。 在另一个实施例中，存储器控制器基于对每个对应于总线的不同相应信号线的电压摆动特性的评估将一个或多个配置命令发送到这种存储器件。

公开(公告)号：US20240404617A1

公开(公告)日：2024-12-05

申请号：US18805118

申请日：2024-08-14

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS ,  Shigeki TOMISHIMA

IPC: G11C29/46 ,  G11C29/10 ,  G11C29/12

Abstract: A system enables an alert signal test mode. The system has an alert signal line between the memory device and the memory controller. The memory device has a register that controls entry into the alert signal test mode. The memory controller sends a command to trigger the memory device to enter the alert signal test mode. In response to the commands, the memory device asserts the alert signal line with an alert signal in response to entry into the alert signal test mode.

公开(公告)号：US20230005526A1

公开(公告)日：2023-01-05

申请号：US17943044

申请日：2022-09-12

Applicant: Intel Corporation

Inventor： Sagar SUTHRAM ,  Abhishek SHARMA ,  Wilfred GOMES ,  Pushkar RANADE ,  Kuljit S. BAINS ,  Tahir GHANI ,  Anand MURTHY

IPC: G11C11/406 ,  H01L25/065 ,  H01L25/18

Abstract: A system can be designed with memory to operate in a low temperature environment. The low temperature memory can be customized for low temperature operation, having a gate stack to adjust a work function of the memory cell transistors to reduce the threshold voltage (Vth) relative to a standard memory device. The reduced temperature can improve the conductivity of other components within the memory, enabling increased memory array sizes, fewer vertical ground channels for stacked devices, and reduced operating power. Based on the differences in the memory, the memory controller can manage access to the memory device with adjusted control parameters based on lower leakage voltage for the memory cells and lower line resistance for the memory array.

公开(公告)号：US20220350715A1

公开(公告)日：2022-11-03

申请号：US17865095

申请日：2022-07-14

Applicant: Intel Corporation

Inventor： Shen ZHOU ,  Cong LI ,  Tai HUANG ,  Kuljit S. BAINS

IPC: G06F11/20

Abstract: A system can respond to detection or prediction of an uncorrectable error (UE) in memory based on fault-aware analysis. The fault-aware analysis enables the system to generate a determination of a specific hardware element of the memory that is faulty. In response to detection of an error, the system can correlate a hardware configuration of the memory device with historical data indicating memory faults for hardware elements of the hardware configuration. Based on a determination of the specific component that likely caused the UE, the system can identify a region of memory associated with the detected UE and mirror the faulty region to a reserved memory space of the memory device for access to data of the faulty region.

公开(公告)号：US20220075689A1

公开(公告)日：2022-03-10

申请号：US17530086

申请日：2021-11-18

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS

IPC: G06F11/10 ,  G06F13/16

Abstract: A memory device that performs internal ECC (error checking and correction) can treat an N-bit channel as two N/2-bit channels for application of ECC. The memory device includes a memory array to store data and prefetches data bits and error checking and correction (ECC) bits from the memory array for a memory access operation. The memory device includes internal ECC hardware to apply ECC, with a first group of a first half the data bits checked by a first half of the ECC bits in parallel with a second group of a second half of the data bits checked by a second half of the ECC bits.

公开(公告)号：US20220012195A1

公开(公告)日：2022-01-13

申请号：US17484427

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Duane E. GALBI ,  Kuljit S. BAINS

IPC: G06F13/16 ,  G06F12/06

Abstract: A memory system has a configurable mapping of address space of a memory array to address of a memory access command. A controller provides command and enable information specific to a memory device. The command and enable information can cause the memory device to apply a traditional mapping of the command address to the address space, or can cause the memory device to apply an address remapping to remap the command address to different address space.

公开(公告)号：US20210286727A1

公开(公告)日：2021-09-16

申请号：US17214749

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Kuljit S. BAINS

IPC: G06F12/0862 ,  G06F12/0879 ,  G06F12/0882 ,  G06F13/16

Abstract: A memory is described. The memory includes row buffer circuitry to store a page. The page is divided into sections, wherein, at least one of the sections of the page is to be sequestered for the storage of meta data, and wherein, a first subset of column address bits is to: 1) define a particular section of the page, other than the at least one sequestered sections of the page, whose data is targeted by a burst access; and, 2) define a field within the at least one of the sequestered sections of the page that stores meta data for the particular section.