公开(公告)号：US09710041B2

公开(公告)日：2017-07-18

申请号：US14812056

申请日：2015-07-29

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Larisa Novakovsky ,  Krishnakanth V. Sistla ,  Vivek Garg ,  Dean Mulla ,  Ashish V. Choubal ,  Erik G. Hallnor ,  Kimberly C. Weier

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/04 ,  G06F9/38 ,  G06F15/17

CPC classification number: G06F1/3203 ,  G06F1/04 ,  G06F1/26 ,  G06F1/263 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/329 ,  G06F1/3293 ,  G06F9/38 ,  G06F15/163 ,  G06F15/17 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/24 ,  Y02D50/20

Abstract: In one embodiment, a processor includes a core to execute instructions and a core perimeter logic coupled to the core. The core perimeter logic may include a fabric interface logic coupled to the core. In turn, the fabric interface logic may include a first storage to store state information of the core when the core is in a low power state, and enable an inter-die interconnect coupled between the core and an uncore to be maintained in an active state during entry of the core into a low power state. Other embodiments are described and claimed.

公开(公告)号：US20170031412A1

公开(公告)日：2017-02-02

申请号：US14812056

申请日：2015-07-29

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Larisa Novakovsky ,  Krishnakanth V. Sistla ,  Vivek Garg ,  Dean Mulla ,  Ashish V. Choubal ,  Erik G. Hallnor ,  Kimberly C. Weier

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/04 ,  G06F1/26 ,  G06F1/263 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/329 ,  G06F1/3293 ,  G06F9/38 ,  G06F15/163 ,  G06F15/17 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/24 ,  Y02D50/20

Abstract: In one embodiment, a processor includes a core to execute instructions and a core perimeter logic coupled to the core. The core perimeter logic may include a fabric interface logic coupled to the core. In turn, the fabric interface logic may include a first storage to store state information of the core when the core is in a low power state, and enable an inter-die interconnect coupled between the core and an uncore to be maintained in an active state during entry of the core into a low power state. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括执行指令的核心和耦合到核心的核心周边逻辑。 核心周界逻辑可以包括耦合到核的结构接口逻辑。 反过来，结构接口逻辑可以包括第一存储器，以在核心处于低功率状态时存储核心的状态信息，并且使得耦合在核心和核心之间的管芯间互连能够被维持在活动状态 在核心进入低功率状态期间。 描述和要求保护其他实施例。

公开(公告)号：US20160342515A1

公开(公告)日：2016-11-24

申请号：US15162707

申请日：2016-05-24

Applicant: Intel Corporation

Inventor： Larisa Novakovsky ,  Joseph Nuzman ,  Alexander Gendler

IPC: G06F12/0811 ,  G06F12/0831

CPC classification number: G06F12/0811 ,  G06F12/0804 ,  G06F12/0831 ,  G06F12/0837 ,  G06F12/0891 ,  G06F2212/283 ,  G06F2212/621

Abstract: A method for determining an inclusion policy includes determining a ratio of a capacity of a large cache to a capacity of a core cache in a cache subsystem of a processor and selecting an inclusive policy as the inclusion policy for the cache subsystem in response to the cache ratio exceeding an inclusion threshold. The method may further include selecting a non-inclusive policy in response to the cache ratio not exceeding the inclusion threshold and, responsive to a cache transaction resulting in a cache miss, performing an inclusion operation that invokes the inclusion policy.

Abstract translation: 用于确定包含策略的方法包括确定大型缓存的容量与处理器的高速缓存子系统中的核心高速缓存的容量的比率，并且选择包含策略作为响应于高速缓存的高速缓存子系统的包含策略 比例超过包含阈值。 该方法还可以包括响应于不超过包含阈值的高速缓存比率选择不包含策略，并且响应于导致高速缓存未命中的高速缓存事务，执行调用包含策略的包含操作。

公开(公告)号：US09378148B2

公开(公告)日：2016-06-28

申请号：US13843315

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Larisa Novakovsky ,  Joseph Nuzman ,  Alexander Gendler

IPC: G06F12/0891 ,  G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0804 ,  G06F12/0831 ,  G06F12/0837 ,  G06F12/0891 ,  G06F2212/283 ,  G06F2212/621

Abstract: A method for determining an inclusion policy includes determining a ratio of a capacity of a large cache to a capacity of a core cache in a cache subsystem of a processor and selecting an inclusive policy as the inclusion policy for the cache subsystem in response to the cache ratio exceeding an inclusion threshold. The method may further include selecting a non-inclusive policy in response to the cache ratio not exceeding the inclusion threshold and, responsive to a cache transaction resulting in a cache miss, performing an inclusion operation that invokes the inclusion policy.

Abstract translation: 用于确定包含策略的方法包括确定大型缓存的容量与处理器的高速缓存子系统中的核心高速缓存的容量的比率，并且选择包含策略作为响应于高速缓存的高速缓存子系统的包含策略 比例超过包含阈值。 该方法还可以包括响应于不超过包含阈值的高速缓存比率选择不包含策略，并且响应于导致高速缓存未命中的高速缓存事务，执行调用包含策略的包含操作。

公开(公告)号：US11614939B2

公开(公告)日：2023-03-28

申请号：US17359337

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Andreas Kleen ,  Gilbert Neiger ,  Beeman Strong ,  Jason Brandt ,  Rupin Vakharwala ,  Jeff Huxel ,  Larisa Novakovsky ,  Ido Ouziel ,  Sarathy Jayakumar

IPC: G06F9/30 ,  G06F15/80 ,  G06F9/50 ,  G06F9/48

Abstract: An apparatus and method for processing non-maskable interrupt source information. For example, one embodiment of a processor comprises: a plurality of cores comprising execution circuitry to execute instructions and process data; local interrupt circuitry comprising a plurality of registers to store interrupt-related data including non-maskable interrupt (NMI) data related to a first NMI; and non-maskable interrupt (NMI) processing mode selection circuitry, responsive to a request, to select between at least two NMI processing modes to process the first NMI including: a first NMI processing mode in which the plurality of registers are to store first data related to a first NMI, wherein no NMI source information related to a source of the NMI is included in the first data, and a second NMI processing mode in which the plurality of registers are to store both the first data related to the first NMI and second data comprising NMI source information indicating the NMI source.

公开(公告)号：US10775434B2

公开(公告)日：2020-09-15

申请号：US16142591

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Michael Mishaeli ,  Larisa Novakovsky ,  Edward Brazil ,  Alexander Gendler

IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/319 ,  G06F1/3203 ,  G06F11/27

Abstract: In one embodiment, a processor includes a scan system controller to control test operations on the processor in response to test commands from an external test entity, and at least one core to execute instructions. The processor may further include a field scan controller to control a field test mode of the processor to perform a self-test of the at least one core during field operation, where the field scan controller is to obtain a test pattern from an external memory and cause the scan system controller to test circuitry of the first subsystem using the test pattern. Other embodiments are described and claimed.

公开(公告)号：US20180095883A1

公开(公告)日：2018-04-05

申请号：US15283337

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Leon Polishuk ,  Pavel Konev ,  Larisa Novakovsky ,  Julius Mandelblat

IPC: G06F12/0866 ,  G06F9/44

CPC classification number: G06F9/4401 ,  G06F12/126

Abstract: Systems and methods are disclosed for initialization of a processor. Embodiments relate to alleviating any BIOS code size limitation. In one example, a system includes a memory having stored thereon a basic input/output system (BIOS) program comprising a readable code region and a readable and writeable data stack, a circuit coupled to the memory and to: read, during a boot mode and while using a cache as RAM (CAR), at least one datum from each cache line of the data stack, and write at least one byte of each cache line of the data stack to set a state of each cache line of the data stack to modified, enter a no-modified-data-eviction mode to protect modified data from eviction, and to allow eviction and replacement of readable data, and begin reading from the readable code region and executing the BIOS program after entering the no-modified-data-eviction mode.

公开(公告)号：US09360924B2

公开(公告)日：2016-06-07

申请号：US13904055

申请日：2013-05-29

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Larisa Novakovsky ,  Ariel Sabba ,  Niv Tokman

IPC: G06F1/26 ,  G06F1/32 ,  G06F12/08

CPC classification number: G06F1/3275 ,  G06F1/3206 ,  G06F12/0811 ,  G06F2201/885 ,  Y02D10/14

Abstract: In an embodiment, a processor includes a plurality of cores and a cache unit reserved for a first core of the plurality of cores. The cache unit may include a first cache slice, a second cache slice, and power logic to switch operation of the cache unit between a first operating mode and a second operating mode. The first operating mode may include use of both the first cache slice and the second cache slice. The second operating mode may include use of the first cache slice and disabling the second cache slice. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括多个核心和为多个核心中的第一核心预留的高速缓存单元。 高速缓存单元可以包括第一高速缓存片，第二高速缓存片和用于在第一操作模式和第二操作模式之间切换高速缓存单元的操作的电源逻辑。 第一操作模式可以包括使用第一高速缓存片和第二高速缓存片。 第二操作模式可以包括使用第一高速缓存片并禁用第二高速缓存片。 描述和要求保护其他实施例。