公开(公告)号：US20190334020A1

公开(公告)日：2019-10-31

申请号：US16349955

申请日：2016-12-14

Applicant: Intel Corporation

Inventor： Payam Amin ,  Nicole K. Thomas ,  James S. Clarke ,  Jessica M. Torres ,  Ravi Pillarisetty ,  Hubert C. George ,  Kanwaljit Singh ,  Van H. Le ,  Jeanette M. Roberts ,  Roman Caudillo ,  Zachary R. Yoscovits ,  David J. Michalak

IPC: H01L29/775 ,  H01L29/12 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02 ,  G06N10/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum processing device may include: a quantum well stack having alternatingly arranged relaxed and strained layers; and a plurality of gates disposed above the quantum well stack to control quantum dot formation in the quantum well stack.

公开(公告)号：US20190273197A1

公开(公告)日：2019-09-05

申请号：US16347097

申请日：2016-12-27

Applicant: Intel Corporation

Inventor： Jeanette M. Roberts ,  Adel A. Elsherbini ,  Shawna Liff ,  Johanna M. Swan ,  Roman Caudillo ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  Ravi Pillarisetty ,  Hubert C. George ,  James S. Clarke

IPC: H01L39/04 ,  G06N10/00 ,  H01L39/02 ,  H01L39/22 ,  H01L39/24

Abstract: One superconducting qubit device package disclosed herein includes a die having a first face and an opposing second face, and a package substrate having a first face and an opposing second face. The die includes a quantum device including a plurality of superconducting qubits and a plurality of resonators on the first face of the die, and a plurality of conductive pathways coupled between conductive contacts at the first face of the die and associated ones of the plurality of superconducting qubits or of the plurality of resonators. The second face of the package substrate also includes conductive contacts. The device package further includes first level interconnects disposed between the first face of the die and the second face of the package substrate, coupling the conductive contacts at the first face of the die with associated conductive contacts at the second face of the package substrate.

公开(公告)号：US10319896B2

公开(公告)日：2019-06-11

申请号：US15637682

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Javier A. Falcon ,  Adel A. Elsherbini ,  Johanna M. Swan ,  Shawna M. Liff ,  Ye Seul Nam ,  James S. Clarke ,  Jeanette M. Roberts ,  Roman Caudillo

IPC: H01L29/06 ,  H01L29/08 ,  H01L31/0256 ,  H01L39/22 ,  H01R3/00 ,  H05K1/00 ,  H05K9/00 ,  H01L39/04 ,  H01L25/16 ,  H01L23/538 ,  H01L23/66 ,  H01L23/552 ,  H01L39/02 ,  H01L39/24 ,  H01P3/08 ,  H01P11/00 ,  H05K1/02 ,  G06N99/00 ,  G06N10/00

Abstract: Disclosed herein are shielded interconnects, as well as related methods, assemblies, and devices. In some embodiments, a shielded interconnect may be included in a quantum computing (QC) assembly. For example, a QC assembly may include a quantum processing die; a control die; and a flexible interconnect electrically coupling the quantum processing die and the control die, wherein the flexible interconnect includes a plurality of transmission lines and a shield structure to mitigate cross-talk between the transmission lines.

公开(公告)号：US20190044051A1

公开(公告)日：2019-02-07

申请号：US16102780

申请日：2018-08-14

Applicant: Intel Corporation

Inventor： Roman Caudillo ,  Lester Lampert ,  David J. Michalak ,  Jeanette M. Roberts ,  Ravi Pillarisetty ,  Hubert C. George ,  Nicole K. Thomas ,  James S. Clarke

IPC: H01L39/22 ,  H01L39/02 ,  H01L39/24 ,  H01L27/18 ,  H01L39/04 ,  G06N99/00

Abstract: Embodiments of the present disclosure relate to quantum circuit assemblies implementing superconducting qubits, e.g., transmons, in which SQUID loops and portions of FBLs configured to magnetically couple to the SQUID loops extend substantially vertically. In contrast to conventional implementations, for a vertical SQUID according to various embodiments of the present disclosure, a line that is perpendicular to the SQUID loop is parallel to the qubit substrate. A corresponding FBL is also provided in a vertical arrangement, in order to achieve efficient magnetic coupling to the vertical SQUID loop, by ensuring that at least a portion of the FBL designed to conduct current responsible for generating magnetic field for tuning qubit frequency is substantially perpendicular to the substrate.

公开(公告)号：US20190044047A1

公开(公告)日：2019-02-07

申请号：US15899918

申请日：2018-02-20

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Javier A. Falcon ,  Roman Caudillo ,  James S. Clarke

IPC: H01L39/04 ,  H01L39/02 ,  H01L39/22 ,  H01L39/24 ,  G06N99/00

Abstract: An exemplary superconducting qubit device package includes a qubit die housing a superconducting qubit device that includes at least one resonator, and a package substrate, each having a first face and an opposing second face. The resonator is disposed on the first face of the qubit die. The first face of the qubit die faces and is attached to the second face of the package substrate by first level interconnects. The second face of the package substrate includes a superconductor facing at least portions of the resonator. Such a package architecture may advantageously allow reducing design complexity and undesired coupling, enable inclusion of larger numbers of qubit devices in the qubit die of the package, reduce potential negative impact of the materials used in the package substrate on resonator performance, and limit some sources of qubit decoherence.

公开(公告)号：US20190044045A1

公开(公告)日：2019-02-07

申请号：US15924410

申请日：2018-03-19

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  James S. Clarke ,  Jessica M. Torres ,  Lester Lampert ,  Ravi Pillarisetty ,  Hubert C. George ,  Kanwaljit Singh ,  Jeanette M. Roberts ,  Roman Caudillo ,  Zachary R. Yoscovits ,  David J. Michalak

IPC: H01L39/02 ,  H01L39/04 ,  H01L39/22 ,  H01L39/24 ,  H03K17/92 ,  G06N99/00

CPC classification number: H01L39/025 ,  B82Y10/00 ,  G06N10/00 ,  H01L29/127 ,  H01L29/423 ,  H01L29/66439 ,  H01L29/66977 ,  H01L29/66984 ,  H01L29/7613 ,  H01L39/045 ,  H01L39/223 ,  H01L39/249 ,  H01L39/2493 ,  H03K17/92

Abstract: Embodiments of the present disclosure describe use of isotopically purified materials in donor- or acceptor-based spin qubit devices and assemblies. An exemplary spin qubit device assembly may include a semiconductor host layer that includes an isotopically purified material, a dopant atom in the semiconductor host layer, and a gate proximate to the dopant atom. An isotopically purified material may include a lower atomic-percent of isotopes with nonzero nuclear spin than the natural abundance of those isotopies in the non-isotopically purified material. Reducing the presence of isotopes with nonzero nuclear spin in a semiconductor host layer may improve qubit coherence and thus performance of spin qubit devices and assemblies.

公开(公告)号：US20190043975A1

公开(公告)日：2019-02-07

申请号：US16017031

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Hubert C. George ,  David J. Michalak ,  Ravi Pillarisetty ,  Lester Lampert ,  James S. Clarke ,  Zachary R. Yoscovits ,  Nicole K. Thomas ,  Roman Caudillo ,  Kanwaljit Singh ,  Jeanette M. Roberts

IPC: H01L29/778 ,  H01L29/12 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/15 ,  H01L27/088 ,  H01L29/10 ,  G06N99/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; a first dielectric material around a bottom portion of the fin; and a second dielectric material around a top portion of the fin, wherein the second dielectric material is different from the first dielectric material.

公开(公告)号：US20190043968A1

公开(公告)日：2019-02-07

申请号：US15924407

申请日：2018-03-19

Applicant: Intel Corporation

Inventor： Lester Lampert ,  James S. Clarke ,  Jeanette M. Roberts ,  Ravi Pillarisetty ,  David J. Michalak ,  Kanwaljit Singh ,  Roman Caudillo ,  Hubert C. George ,  Zachary R. Yoscovits ,  Nicole K. Thomas

IPC: H01L29/66 ,  H01L29/82 ,  H01L29/49 ,  H01L21/265 ,  H01L29/40 ,  G06N99/00

Abstract: Embodiments of the present disclosure describe a method of fabricating spin qubit device assemblies that utilize dopant-based spin qubits, i.e. spin qubit devices which operate by including a donor or an acceptor dopant atom in a semiconductor host layer. The method includes, first, providing a pair of gate electrodes over a semiconductor host layer, and then providing a window structure between the first and second gate electrodes, the window structure being a continuous solid material extending between the first and second electrodes and covering the semiconductor host layer except for an opening through which a dopant atom is to be implanted in the semiconductor host layer. By using a defined gate-first process, the method may address the scalability challenges and create a deterministic path for fabricating dopant-based spin qubits in desired locations, promoting wafer-scale integration of dopant-based spin qubit devices for use in quantum computing devices.

公开(公告)号：US20190043951A1

公开(公告)日：2019-02-07

申请号：US16015087

申请日：2018-06-21

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ravi Pillarisetty ,  Payam Amin ,  Roza Kotlyar ,  Patrick H. Keys ,  Hubert C. George ,  Kanwaljit Singh ,  James S. Clarke ,  David J. Michalak ,  Lester Lampert ,  Zachary R. Yoscovits ,  Roman Caudillo ,  Jeanette M. Roberts

IPC: H01L29/12 ,  H01L29/10 ,  H01L29/423 ,  H01L29/165 ,  H01L21/02 ,  H01L29/66 ,  H01L29/778 ,  G06N99/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer and a barrier layer; a first gate metal above the quantum well stack, wherein the barrier layer is between the first gate metal and the quantum well layer; and a second gate metal above the quantum well stack, wherein the barrier layer is between the second gate metal and the quantum well layer, and a material structure of the second gate metal is different from a material structure of the first gate metal.

公开(公告)号：US11721724B2

公开(公告)日：2023-08-08

申请号：US17364985

申请日：2021-07-01

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  James S. Clarke ,  Jessica M. Torres ,  Ravi Pillarisetty ,  Kanwaljit Singh ,  Payam Amin ,  Hubert C. George ,  Jeanette M. Roberts ,  Roman Caudillo ,  David J. Michalak ,  Zachary R. Yoscovits ,  Lester Lampert

IPC: H01L29/12 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/82

CPC classification number: H01L29/122 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66977 ,  H01L29/66984 ,  H01L29/82

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; a gate dielectric above the quantum well stack; and a gate metal above the gate dielectric, wherein the gate dielectric is between the quantum well layer and the gate metal.