公开(公告)号：US20210011741A1

公开(公告)日：2021-01-14

申请号：US17033267

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Katalin Klara Bartfai-Walcott ,  Arkadiusz Berent ,  Vasuki Chilukuri ,  Mark Baldwin ,  Vasudevan Srinivasan ,  Bartosz Gotowalski

IPC: G06F9/445 ,  G06F11/30 ,  H04L9/32 ,  G06F21/10

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to provide device enhancements for software defined silicon implementations are disclosed. Example apparatus disclosed herein include a request interface to receive a request for a timestamp. Disclosed example apparatus also include a property checker to determine a first value of an electrical property of a feature embedded in a silicon product, the feature having electrical properties that change over time. Disclosed example apparatus further include a relative time determiner to calculate a relative time between the request and a previous event based on the first value of the electrical property and a second value of the electrical property, the second value of the electrical property associated with the previous event.

公开(公告)号：US10856102B2

公开(公告)日：2020-12-01

申请号：US16446823

申请日：2019-06-20

Applicant: INTEL CORPORATION

Inventor： Vasudevan Srinivasan ,  Barnes Cooper ,  Tawfik M Rahal-Arabi

IPC: H04W4/38 ,  H04W4/80 ,  H04W4/021 ,  H04L12/26 ,  H04W4/70

Abstract: Embodiments are generally directed to sharing of environmental data for client device usage. An embodiment of a client device includes a processor; an environmental sensor to sense an environmental condition, an output of the sensor being a local environmental sensor value; and a wireless receiver to receive environmental data for a certain proximity area from a second client device according to an environmental data sharing protocol via a wireless network. The environmental data sharing protocol allows receipt of the environmental data without requiring pairing, bonding, or other relationship of client devices.

公开(公告)号：US20180287949A1

公开(公告)日：2018-10-04

申请号：US15472910

申请日：2017-03-29

Applicant: Intel Corporation

Inventor： Mohan J. Kumar ,  Murugasamy K. Nachimuthu ,  Vasudevan Srinivasan

IPC: H04L12/851 ,  H04L12/927 ,  H04L12/24 ,  H04L29/08 ,  G06F9/50

Abstract: A rack system including a plurality of nodes can implement thermal/power throttling, sub-node composition, and processing balancing based on voltage/frequency. In the thermal/power throttling, at least one resource is throttled, based at least in part on a heat event or a power event. In the sub-node composition, a plurality of computing cores is divided into a target number of domains. In the processing balancing based on voltage/frequency, a first core performs a first processing job at a first voltage or frequency, and a second core performs a second processing job at a second voltage or frequency different from the first voltage or frequency.

公开(公告)号：US10079507B2

公开(公告)日：2018-09-18

申请号：US13931442

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Milan Milenkovic ,  Ulf R. Hanebutte ,  Vasudevan Srinivasan

IPC: G05F1/66 ,  H02J13/00 ,  H02J3/38

CPC classification number: H02J13/0079 ,  H02J3/38 ,  Y02E40/72 ,  Y04S10/12

Abstract: Techniques for adaptive demand/response power management. Power consumption and battery charge level of a platform having a battery with a smart power module are monitored. Information indicating the power consumption and battery charge level for the platform is provided to a remote demand/response management device. The remote demand/response management device and the smart power module receive a command to modify one or more power consumption characteristics of the platform. The one or more power consumption characteristics of the platform are to be changed in response to the command.

公开(公告)号：US09898067B2

公开(公告)日：2018-02-20

申请号：US15089350

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Eric Distefano ,  Guy M. Therien ,  Vasudevan Srinivasan ,  Tawfik M. Rahal-Arabi ,  Venkatesh Ramani ,  Ryan D. Wells ,  Stephen H. Gunther ,  Jeremy J. Shrall ,  James G. Hermerding, II

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  G06F1/20

CPC classification number: G06F1/3234 ,  G06F1/206 ,  G06F1/26 ,  Y02D10/16

Abstract: A technique to change a thermal design power (TDP) value. In one embodiment, one or more environmental or user-driven changes may cause a processor's TDP value to be changed. Furthermore, in some embodiments a change in TDP may alter a turbo mode target frequency.

公开(公告)号：US09874922B2

公开(公告)日：2018-01-23

申请号：US14623764

申请日：2015-02-17

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth V. Sistla ,  Vasudevan Srinivasan ,  Eugene Gorbatov ,  Andrew D. Henroid ,  Barnes Cooper ,  David W. Browning ,  Guy M. Therien ,  Neil W. Songer ,  James G. Hermerding, II

IPC: G06F1/32 ,  G06F9/50

CPC classification number: G06F1/3206 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/50 ,  Y02B70/126 ,  Y02D10/171

Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power control logic to receive power capability information from a plurality of devices to couple to the processor and allocate a platform power budget to the devices, set a first power level for the devices at which the corresponding device is allocated to be powered, communicate the first power level to the devices, and dynamically reduce a first power to be allocated to a first device and increase a second power to be allocated to a second device responsive to a request from the second device for a higher power level. Other embodiments are described and claimed.

公开(公告)号：US20170329377A1

公开(公告)日：2017-11-16

申请号：US15668771

申请日：2017-08-04

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Vasudevan Srinivasan ,  Eugene Gorbatov ,  Andrew D. Henroid ,  Barnes Cooper ,  David W. Browning ,  Guy M. Therien ,  Neil W. Songer ,  Krishnakanth V. Sistla ,  James G. Hermerding, II

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/20 ,  G06F15/00

Abstract: In one embodiment, a system includes: a plurality of compute nodes to couple in a chassis; a first shared power supply to provide a baseline power level to the plurality of compute nodes; and an auxiliary power source to provide power to one or more of the plurality of compute nodes during operation at a higher power level than the baseline power level. Other embodiments are described and claimed.

公开(公告)号：US12061930B2

公开(公告)日：2024-08-13

申请号：US17033200

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Katalin Klara Bartfai-Walcott ,  Mark Baldwin ,  Arkadiusz Berent ,  Bartosz Gotowalski ,  Vasuki Chilukuri ,  Vasudevan Srinivasan ,  Justyna Chilczuk ,  Vinila Rose ,  Mariusz Oriol

IPC: G06Q10/10 ,  G06F9/50 ,  G06F21/10 ,  G06F21/72 ,  G06F21/73 ,  G06Q20/12 ,  G06Q30/018 ,  G06Q30/0601 ,  G06Q50/04 ,  G06Q50/18 ,  H04L9/08 ,  H04L9/32

CPC classification number: G06F9/5027 ,  G06F21/105 ,  G06F21/72 ,  G06F21/73 ,  G06Q10/10 ,  G06Q20/1235 ,  G06Q20/127 ,  G06Q30/0609 ,  G06Q50/184 ,  H04L9/0861 ,  H04L9/321 ,  H04L9/3263 ,  H04L9/3268 ,  G05B2219/2205 ,  G05B2219/25395 ,  G05B2219/33088 ,  G06F21/1011 ,  G06F2209/501 ,  G06F2209/504 ,  G06F2209/506 ,  G06F2221/2149 ,  G06Q30/0185 ,  G06Q50/04 ,  G06Q2220/18 ,  H04L9/3278

Abstract: Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement software defined silicon feature licensing are disclosed. Example licensor systems disclosed herein includes a third party verifier to verify one or more credentials included in a request to become an authorized delegated licensor, the request received from a third party. Disclosed example licensor systems also include a feature identifier to identify a feature of a silicon structure which the third party is to be granted the authority to license. Disclosed example licensor systems further include a configuration installation code generator to generate feature configuration installation code, the feature configuration installation code to be used by the third party to generate at least a portion of the license, the portion of the license to be used by a licensee to configure the silicon structure to access the licensed feature, and contents of the feature configuration installation code encrypted to prevent access by the authorized delegated licensor.

公开(公告)号：US11567556B2

公开(公告)日：2023-01-31

申请号：US16833008

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Chris Macnamara ,  John J. Browne ,  Tomasz Kantecki ,  David Hunt ,  Anatoly Burakov ,  Srihari Makineni ,  Nikhil Gupta ,  Ankush Varma ,  Dorit Shapira ,  Vasudevan Srinivasan ,  Bryan T. Butters ,  Shrikant M. Shah

IPC: G06F1/324 ,  G06F1/20 ,  G06F9/50 ,  G06F1/3296

Abstract: Examples herein relate to assigning, by a system agent of a central processing unit (CPU), an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent. Avoiding throttling of the system agent can include maintaining a minimum performance level of the system agent. A minimum performance level of the system agent can be based on a minimum operating frequency. Assigning, by a system agent of a central processing unit, an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent can avoid a thermal limit of the CPU. Avoiding thermal limit of the CPU can include adjusting the operating frequency to the core group to avoid performance indicators of the CPU. A performance indicator can indicate CPU utilization corresponds to Thermal Design Point (TDP).

公开(公告)号：US11301298B2

公开(公告)日：2022-04-12

申请号：US16833595

申请日：2020-03-28

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Nikhil Gupta ,  Vasudevan Srinivasan ,  Krishnakanth Sistla ,  Nilanjan Palit ,  Abhinav Karhu ,  Eugene Gorbatov ,  Eliezer Weissmann

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/54 ,  G06F15/80

Abstract: An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores to be allocated to form a first plurality of logical processors (LPs) to execute threads, wherein one or more logical processors (LPs) are to be associated with each core of the plurality of cores; scheduling guide circuitry to: monitor execution characteristics of the first plurality of LPs and the threads; generate a first plurality of LP rankings, each LP ranking including all or a subset of the plurality of LPs in a particular order; and store the first plurality of LP rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of LPs using the first plurality of LP rankings; a power controller to execute power management code to perform power management operations including independently adjusting frequencies and/or voltages of one or more of the plurality of cores; wherein in response to a core configuration command to deactivate a first core of the plurality of cores, the power controller or privileged program code executed on the processor are to update the memory with an indication of deactivation of the first core, wherein responsive to the indication of deactivation of the first core, the scheduler is to modify the scheduling of the threads.