公开(公告)号：US10332899B2

公开(公告)日：2019-06-25

申请号：US15721703

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Yi Xu ,  Florence Pon ,  Yong She

IPC: H01L27/112 ,  G06F17/50 ,  H01L21/768 ,  H01L23/525 ,  H03K19/177

Abstract: An IC package, comprising a substrate and two or more vertically stacked dies disposed within the substrate, wherein all the edges of the two or more dies are aligned with respect to one another, wherein at least two dies of the two or more vertically stacked dies are coupled directly to one another by at least one wire bonded to the ones of the at least two dies.

公开(公告)号：US11894344B2

公开(公告)日：2024-02-06

申请号：US17714979

申请日：2022-04-06

Applicant: INTEL CORPORATION

Inventor： Zhijun Xu ,  Bin Liu ,  Yong She ,  Zhicheng Ding

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/73 ,  H01L24/92 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: An apparatus comprising: a die stack comprising at least one die pair, the at least one die pair having a first die over a second die, the first die and the second die both having a first surface and a second surface, the second surface of the first die over the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair; wherein the adhesive film comprises an insulating layer and a conductive layer, the insulating layer adhering to the second surface of the first die and the conductive layer adhering to the first surface of the second die.

公开(公告)号：US11881441B2

公开(公告)日：2024-01-23

申请号：US16642815

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Sireesha Gogineni ,  Andrew Kim ,  Yong She ,  Karissa J. Blue

IPC: H01L23/373 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L23/3738 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06506 ,  H01L2225/06568

Abstract: Stacked die semiconductor packages may include a spacer die disposed between stacked dies in the semiconductor package and the semiconductor package substrate. The spacer die translates thermally induced stresses on the solder connections between the substrate and an underlying member, such as a printed circuit board, from electrical structures communicably or conductively coupling the semiconductor package substrate to the underlying structure to mechanical structures that physically couple the semiconductor package to the underlying structure. The footprint area of the spacer die is greater than the sum of the footprint areas of the individual stacked dies in the semiconductor package and less than or equal to the footprint area of the semiconductor package substrate. The spacer die may have nay physical configuration, thickness, shape, or geometry. The spacer die may have a coefficient of thermal expansion similar to that of the lowermost semiconductor die in the die stack.

公开(公告)号：US20220020704A1

公开(公告)日：2022-01-20

申请号：US17391612

申请日：2021-08-02

Applicant: Intel Corporation

Inventor： Yong She ,  Bin Liu ,  Zhicheng Ding ,  Aiping Tan

IPC: H01L23/00 ,  G11C5/04 ,  H01L25/065 ,  H01L27/11524 ,  H01L27/1157

Abstract: A microelectronic device can include a polymer, a semiconductor, and a matching layer. The polymer can include a first coefficient of thermal expansion. The semiconductor can be coupled to the polymer layer. The matching layer can be adjacent the semiconductor, and the matching layer can include a second coefficient of thermal expansion that is about the same as the first coefficient of thermal expansion.

公开(公告)号：US10910347B2

公开(公告)日：2021-02-02

申请号：US16516695

申请日：2019-07-19

Applicant: Intel Corporation

Inventor： Yong She ,  John G. Meyers ,  Zhicheng Ding ,  Richard Patten

IPC: H01L25/065 ,  H01L23/488 ,  H01L23/00 ,  H01L23/49 ,  H01L23/50 ,  H01L25/00 ,  H01L23/538

Abstract: Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.

公开(公告)号：US10770434B2

公开(公告)日：2020-09-08

申请号：US16326330

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Zhicheng Ding ,  Bin Liu ,  Yong She ,  Aiping Tan ,  Li Deng

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/66 ,  H01L23/31

Abstract: A system in package includes a stair-stacked memory module that is stacked vertically with respect to a processor die. A spacer is used adjacent to the processor die to create a bridge for the stair-stacked memory module. Each memory die in the stair-stacked memory module includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the stair-stacked memory module and at least a portion of the processor die.

公开(公告)号：US20190341372A1

公开(公告)日：2019-11-07

申请号：US16516695

申请日：2019-07-19

Applicant: Intel Corporation

Inventor： Yong She ,  John G. Meyers ,  Zhicheng Ding ,  Richard Patten

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/50 ,  H01L23/488 ,  H01L23/49 ,  H01L25/00

Abstract: Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.

公开(公告)号：US09778688B2

公开(公告)日：2017-10-03

申请号：US14779300

申请日：2014-11-12

Applicant: INTEL CORPORATION

Inventor： Jiamiao Tang ,  Junfeng Zhao ,  Michael P. Skinner ,  Yong She ,  Jiun Hann Sir ,  Bok Eng Cheah ,  Shanggar Periaman ,  Kooi Chi Ooi ,  Yen Hsiang Chew

IPC: H01L23/48 ,  G06F1/16 ,  H01L23/31 ,  A41B1/00 ,  A41D1/06 ,  A41D1/08 ,  A41F9/00 ,  A43B3/00 ,  A43B7/14 ,  A44C5/00 ,  A44C15/00 ,  F03G5/06 ,  G06F1/18 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H02J1/14 ,  H05K1/18

CPC classification number: G06F1/163 ,  A41B1/00 ,  A41D1/002 ,  A41D1/06 ,  A41D1/08 ,  A41F9/002 ,  A43B3/001 ,  A43B3/0015 ,  A43B7/141 ,  A44C5/0015 ,  A44C15/005 ,  F03G5/06 ,  G06F1/189 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3135 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/5387 ,  H01L23/562 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/73257 ,  H01L2924/0002 ,  H01L2924/181 ,  H02J1/14 ,  H05K1/189 ,  H05K2201/05 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package. In embodiments, an integrated circuit (IC) package may include a flexible substrate. The flexible substrate may have a plurality of dies coupled therewith. The IC package may include a first encapsulation material, having a first rigidity, disposed on the flexible substrate to at least partially encapsulate each die of the plurality dies. The IC package may further include a second encapsulation material, having a second rigidity, disposed on the flexible substrate. In embodiments, the second rigidity and the first rigidity are different from one another. Other embodiments may be described and/or claimed.

公开(公告)号：US12027496B2

公开(公告)日：2024-07-02

申请号：US17424839

申请日：2019-02-22

Applicant: Intel Corporation

Inventor： Jianfeng Hu ,  Zhicheng Ding ,  Yong She ,  Zhijun Xu

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/26152 ,  H01L2224/32145 ,  H01L2224/32237 ,  H01L2224/33181 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2224/73215 ,  H01L2224/73263 ,  H01L2924/35121

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a package substrate with a plurality of cavities, and a plurality of adhesives in the cavities of the package substrate. The semiconductor package also includes a plurality of stacked dies over the adhesives and the package substrate, where the stacked dies are coupled to the adhesives with spacers. The spacers may be positioned below outer edges of the stacked dies. The adhesives may include a plurality of films. The semiconductor package may further include a plurality of interconnects coupled to the stacked dies and package substrate, a plurality of electrical components on the package substrate, a mold layer over the stacked dies, interconnects, spacers, adhesives, and electrical components, and a plurality of adhesive layers coupled to the plurality of stacked dies, where one of the adhesive layers couples the stacked dies to the spacers.

公开(公告)号：US11990395B2

公开(公告)日：2024-05-21

申请号：US17425227

申请日：2019-02-22

Applicant: Intel Corporation

Inventor： Xiaoying Tang ,  Zhicheng Ding ,  Bin Liu ,  Yong She ,  Zhijun Xu

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/1319 ,  H01L2224/14179 ,  H01L2224/16227 ,  H01L2224/27849 ,  H01L2224/81815 ,  H01L2924/15311

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a package substrate with a top surface, a corner portion, and a plurality of solder balls on the top surface of the package substrate. The semiconductor package also includes a pattern on the corner portion of the package substrate. The pattern may have a width substantially equal to a width of the solder balls. The pattern may also include a continuous line having solder materials. The semiconductor package may include a plurality of conductive pads on the package substrate. The conductive pads may be coupled to the pattern. The pattern may have a z-height that is substantially equal to a z-height of the solder balls, and have one or more outer edges, where the outer edges of the pattern are sidewalls. The sidewalls of the pattern may be substantially vertical or tapered sidewalls.