公开(公告)号：US10658201B2

公开(公告)日：2020-05-19

申请号：US15935128

申请日：2018-03-26

Applicant: Intel IP Corporation

Inventor： Sonja Koller ,  Georg Seidemann ,  Bernd Waidhas

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/498

Abstract: A method for forming a carrier substrate for a semiconductor device, the method includes providing a substrate layer including conductive particles embedded in an electrically insulating material and localized heating of the substrate layer along a desired trace by a laser to form a conductive trace of merged particles along the desired trace.

公开(公告)号：US10553538B2

公开(公告)日：2020-02-04

申请号：US16152221

申请日：2018-10-04

Applicant: Intel IP Corporation

Inventor： Klaus Jürgen Reingruber ,  Sven Albers ,  Christian Georg Geissler ,  Georg Seidemann ,  Bernd Waidhas ,  Thomas Wagner ,  Marc Dittes

IPC: H01L23/538 ,  H01L23/528 ,  H01L23/498 ,  H01L23/00 ,  C25D5/02 ,  C25D5/10 ,  C25D5/48 ,  C25D5/54 ,  C25D7/12 ,  H01L23/522 ,  H05K1/02 ,  H05K1/11

Abstract: Semiconductor packages having variable redistribution layer thicknesses are described. In an example, a semiconductor package includes a redistribution layer on a dielectric layer, and the redistribution layer includes first conductive traces having a first thickness and second conductive traces having a second thickness. The first thickness may be different than the second thickness, e.g., the first thickness may be less than the second thickness.

公开(公告)号：US20190341371A1

公开(公告)日：2019-11-07

申请号：US16515979

申请日：2019-07-18

Applicant: Intel IP Corporation

Inventor： Bernd Waidhas ,  Georg Seidemann ,  Andreas Augustin ,  Laurent Millou ,  Andreas Wolter ,  Reinhard Mahnkopf ,  Stephan Stoeckl ,  Thomas Wagner

IPC: H01L25/065 ,  H01L25/10 ,  H01L21/48 ,  H01L23/48 ,  H01L25/00

Abstract: A semiconductive device stack, includes a baseband processor die with an active surface and a backside surface, and a recess in the backside surface. A recess-seated device is disposed in the recess, and a through-silicon via in the baseband processor die couples the baseband processor die at the active surface to the recess-seated die at the recess. A processor die is disposed on the baseband processor die backside surface, and a memory die is disposed on the processor die. The several dice are coupled by through-silicon via groups.

公开(公告)号：US20190312016A1

公开(公告)日：2019-10-10

申请号：US15945648

申请日：2018-04-04

Applicant: Intel IP Corporation

Inventor： David O'Sullivan ,  Georg Seidemann ,  Richard Patten ,  Bernd Waidhas

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a mold over and around a first die and a first via. The semiconductor package has a conductive pad of a first redistribution layer disposed on a top surface of the first die and/or a top surface of the mold. The semiconductor package includes a second die having a solder ball coupled to a die pad on a bottom surface of the second die, where the solder ball of the second die is coupled to the first redistribution layer. The first redistribution layer couples the second die to the first die, where the second die has a first edge and a second edge, and where the first edge is positioned within a footprint of the first die and the second edge is positioned outside the footprint of the first die.

公开(公告)号：US20190207027A1

公开(公告)日：2019-07-04

申请号：US16298680

申请日：2019-03-11

Applicant: Intel IP Corporation

Inventor： Bernd Waidhas ,  Sonja Koller ,  Georg Seidemann

IPC: H01L29/78 ,  H01L23/50 ,  H01L23/00 ,  H01L29/66 ,  H01L23/498

CPC classification number: H01L29/7835 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/06 ,  H01L29/66659

Abstract: A power mesh-on-die apparatus includes a solder trace that enhances current flow for a power source trace between adjacent power bumps. The solder trace is also applied between power drain bumps on a power drain trace.

公开(公告)号：US20190198448A1

公开(公告)日：2019-06-27

申请号：US15852908

申请日：2017-12-22

Applicant: Intel IP Corporation

Inventor： Sonja Koller ,  Georg Seidemann ,  Bernd Waidhas

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/552 ,  H01L23/498 ,  H01L23/373 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L23/5387 ,  H01L23/3675 ,  H01L23/3733 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/5385 ,  H01L23/552 ,  H01L24/32 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/83851

Abstract: A semiconductor device package includes an anisotropically conductive flexible film including a plurality of electrically conductive corridors. The film is coupled to make electronic and also heat-transfer contact to a semiconductive device.

公开(公告)号：US10665522B2

公开(公告)日：2020-05-26

申请号：US15853173

申请日：2017-12-22

Applicant: Intel IP Corporation

Inventor： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L21/66 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.

公开(公告)号：US10546817B2

公开(公告)日：2020-01-28

申请号：US15857189

申请日：2017-12-28

Applicant: Intel IP Corporation

Inventor： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

IPC: H01L25/00 ,  H01L23/538 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L25/16

Abstract: A face-up fan-out electronic package including at least one passive component located on a support. The electronic package can include a die. The die can include a plurality of conductive pillars having a proximal end communicatively coupled to the first side of the die and a distal end opposite the proximal end. A mold can at least partially surround the die. The mold can include a first surface that is coplanar with the distal end of the conductive pillars and a second surface opposing the first surface. In an example, the passive component can include a body and a lead. The passive component can be located within the mold. The lead can be coplanar with the first surface, and the body can be located at a distance from the second surface. The support can be located between the body and the second surface.

公开(公告)号：US20190393154A1

公开(公告)日：2019-12-26

申请号：US16458675

申请日：2019-07-01

Applicant: Intel IP Corporation

Inventor： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498

Abstract: An electronic device may include a semiconductor die. The electronic device may include a first routing layer. The first routing layer may be coupled to the semiconductor die. A first plurality of routing traces may be in electrical communication with the semiconductor die. The first plurality of routing traces may be positioned within a first routing footprint. The first routing footprint may have a width greater than a width of the semiconductor die.A second routing layer may be coupled to the first routing layer. A second plurality of routing traces may be in electrical communication with the first plurality of routing traces. The second plurality of routing traces may be positioned within a second routing footprint. The second routing footprint may have a width greater than the width of the first routing footprint.

公开(公告)号：US20190355659A1

公开(公告)日：2019-11-21

申请号：US15981830

申请日：2018-05-16

Applicant: Intel IP Corporation

Inventor： David O'Sullivan ,  Bernd Waidhas ,  Thomas Huber

IPC: H01L23/522 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/28

Abstract: Fan Out Package-On-Package (PoP) assemblies in which a second chip is adhered to a non-active side of a first chip. An active side of the first chip embedded in a first package material may be electrically coupled through one or more redistribution layers that fan out to package interconnects on a first side of the POP. A second chip may be adhered, with a second package material, to the non-active side of the first chip. An active side of the second chip may be electrically coupled to the package interconnects through a via structure extending through the first package material. Second interconnects between the second chip, or a package thereof, may contact the via structure. Use of the second package material as an adhesive may improve positional stability of the second chip to facilitate wafer-level assembly techniques.