公开(公告)号：US10446456B2

公开(公告)日：2019-10-15

申请号：US15865842

申请日：2018-01-09

Applicant: INVENSAS CORPORATION

Inventor： Hong Shen ,  Charles G. Woychik ,  Arkalgud R. Sitaram

IPC: H01L23/31 ,  H01L23/055 ,  H01L21/56 ,  H01L21/288 ,  H01L21/768 ,  H01L23/498 ,  H01L25/065 ,  H01L25/00 ,  H01L23/04 ,  H01L23/14 ,  H01L23/367 ,  H01L23/00 ,  H01L23/48 ,  H01L23/538 ,  H01L21/48 ,  H01L23/10

Abstract: Dies (110) with integrated circuits are attached to a wiring substrate (120), possibly an interposer, and are protected by a protective substrate (410) attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). In some embodiments, each cavity surface puts pressure on the die to strengthen the mechanical attachment of the die the wiring substrate, to provide good thermal conductivity between the dies and the ambient (or a heat sink), to counteract the die warpage, and possibly reduce the vertical size. The protective substrate may or may not have its own circuitry connected to the dies or to the wiring substrate. Other features are also provided.

公开(公告)号：US10440822B2

公开(公告)日：2019-10-08

申请号：US15682049

申请日：2017-08-21

Applicant: Invensas Corporation

Inventor： Bong-Sub Lee ,  Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Liang Wang ,  Laura Wills Mirkarimi ,  Arkalgud R. Sitaram

IPC: H05K13/04 ,  H05K1/09 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K1/16 ,  H05K3/18

Abstract: Interposer circuitry (130) is formed on a possibly sacrificial substrate (210) from a porous core (130′) covered by a conductive coating (130″) which increases electrical conductance. The core is printed from nanoparticle ink. Then a support (120S) is formed, e.g. by molding, to mechanically stabilize the circuitry. A magnetic field can be used to stabilize the circuitry while the circuitry or the support are being formed. Other features are also provided.

公开(公告)号：US10283484B2

公开(公告)日：2019-05-07

申请号：US15164179

申请日：2016-05-25

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Arkalgud R. Sitaram

IPC: H05K3/07 ,  H01L23/00 ,  H01L21/683 ,  H01L23/367 ,  H01L23/373 ,  H01L25/065 ,  C25F3/12 ,  C25F3/14 ,  H05K1/02 ,  H05K1/11 ,  H01L21/48 ,  H01L23/498

Abstract: A mask is formed over a first conductive portion of a conductive layer to expose a second conductive portion of the conductive layer. An electrolytic process is performed to remove conductive material from a first region and a second region of the second conductive portion. The second region is aligned with the mask relative to an electric field applied by the electrolytic process. The second region separates the first region of the second conductive portion from the first conductive portion. The electrolytic process is concentrated relative to the second region such that removal occurs at a relatively higher rate in the second region than in the first region.

公开(公告)号：US10177086B2

公开(公告)日：2019-01-08

申请号：US15952935

申请日：2018-04-13

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Hong Shen ,  Zhuowen Sun ,  Liang Wang ,  Guilian Gao

IPC: H01L23/04 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H01L21/8234

Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

公开(公告)号：US10032751B2

公开(公告)日：2018-07-24

申请号：US15247705

申请日：2016-08-25

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Arkalgud R. Sitaram

IPC: H01L21/30 ,  H01L21/46 ,  H01L25/065 ,  H01L21/02 ,  H01L21/311 ,  H01L23/00 ,  H01L25/00 ,  H01L23/64

Abstract: Capacitive coupling of integrated circuit die components and other conductive areas is provided. Each component to be coupled has a surface that includes at least one conductive area, such as a metal pad or plate. An ultrathin layer of dielectric is formed on at least one surface to be coupled. When the two components, e.g., one from each die, are permanently contacted together, the ultrathin layer of dielectric remains between the two surfaces, forming a capacitor or capacitive interface between the conductive areas of each respective component. The ultrathin layer of dielectric may be composed of multiple layers of various dielectrics, but in one implementation, the overall thickness is less than approximately 50 nanometers. The capacitance per unit area of the capacitive interface formed depends on the particular dielectric constants κ of the dielectric materials employed in the ultrathin layer and their respective thicknesses. Electrical and grounding connections can be made at the edge of the coupled stack.

公开(公告)号：US09899281B2

公开(公告)日：2018-02-20

申请号：US15265148

申请日：2016-09-14

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Charles G. Woychik ,  Arkalgud R. Sitaram

IPC: H01L23/498 ,  H01L23/055 ,  H01L23/31 ,  H01L21/56 ,  H01L21/288 ,  H01L21/768 ,  H01L25/065 ,  H01L25/00 ,  H01L23/04 ,  H01L23/14 ,  H01L23/367 ,  H01L23/00 ,  H01L23/48 ,  H01L23/538 ,  H01L21/48 ,  H01L23/10

CPC classification number: H01L23/055 ,  H01L21/2885 ,  H01L21/4803 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/04 ,  H01L23/10 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/315 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Dies (110) with integrated circuits are attached to a wiring substrate (120), possibly an interposer, and are protected by a protective substrate (410) attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). In some embodiments, each cavity surface puts pressure on the die to strengthen the mechanical attachment of the die the wiring substrate, to provide good thermal conductivity between the dies and the ambient (or a heat sink), to counteract the die warpage, and possibly reduce the vertical size. The protective substrate may or may not have its own circuitry connected to the dies or to the wiring substrate. Other features are also provided.

公开(公告)号：US09824974B2

公开(公告)日：2017-11-21

申请号：US15364534

申请日：2016-11-30

Applicant: Invensas Corporation

Inventor： Guilian Gao ,  Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Hong Shen ,  Arkalgud R. Sitaram ,  Liang Wang ,  Akash Agrawal ,  Rajesh Katkar

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/683 ,  H01L23/498 ,  H01L23/14 ,  H01L23/15

CPC classification number: H01L23/5385 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48105 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49097 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: Die (110) and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer (120) or some other structure (e.g. another integrated circuit) and are covered by an encapsulant (160). Then the interposer is thinned from below. Before encapsulation, a layer (410) more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.

公开(公告)号：US09548273B2

公开(公告)日：2017-01-17

申请号：US14704714

申请日：2015-05-05

Applicant: Invensas Corporation

Inventor： Guilian Gao ,  Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Hong Shen ,  Arkalgud R. Sitaram ,  Liang Wang ,  Akash Agrawal ,  Rajesh Katkar

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/5385 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48105 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49097 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: Die (110) and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer (120) or some other structure (e.g. another integrated circuit) and are covered by an encapsulant (160). Then the interposer is thinned from below. Before encapsulation, a layer (410) more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.

Abstract translation: 模具（110）和/或未开封的晶片和/或多芯片模块（MCM）被附接在插入器（120）或一些其它结构（例如另一集成电路）的顶部上并被密封剂（160）覆盖。 然后插入器从下面变薄。 在封装之前，在封装周围的插入件周围形成比密封剂更刚性的层（410），以通过机械工艺（例如CMP）来减小或消除插入件在裸片间的凹陷。 还提供其他功能。

公开(公告)号：US20160268205A1

公开(公告)日：2016-09-15

申请号：US15158963

申请日：2016-05-19

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar ,  Charles G. Woychik ,  Guilian Gao ,  Arkalgud R. Sitaram

IPC: H01L23/532 ,  H01L23/498 ,  H01L25/065 ,  H01L21/768

CPC classification number: H01L23/5328 ,  H01L21/76838 ,  H01L21/7684 ,  H01L21/76898 ,  H01L23/49811 ,  H01L23/5226 ,  H01L24/83 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/4823 ,  H01L2224/73203 ,  H01L2224/73257 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2924/014

Abstract: An interconnect (124) suitable for attachment of integrated circuit assemblies to each other comprises a polymer member (130) which is conductive and/or is coated with a conductive material (144). Such interconnects replace metal bond wires in some embodiments. Other features are also provided.

公开(公告)号：US20160247758A1

公开(公告)日：2016-08-25

申请号：US14629271

申请日：2015-02-23

Applicant: Invensas Corporation

Inventor： Hong Shen ,  Liang Wang ,  Arkalgud R. Sitaram

IPC: H01L23/522 ,  H01L23/532

CPC classification number: H01L24/09 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/53209 ,  H01L24/89 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/08168 ,  H01L2224/08501 ,  H01L2224/73204 ,  H01L2224/80487 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/05442 ,  H01L2924/1304 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3511

Abstract: Two microelectronic components (110, 120), e.g. a die and an interposer, are bonded to each other. One of the components' contact pads (110C) include metal, and the other component has silicon (410) which reacts with the metal to form metal silicide (504). Then a hole (510) is made through one of the components to reach the metal silicide and possibly even the unreacted metal (110C) of the other component. The hole is filled with a conductor (130), possibly metal, to provide a conductive via that can be electrically coupled to contact pads (120C.B) attachable to other circuit elements or microelectronic components, e.g. to a printed circuit board.

Abstract translation: 两个微电子部件（110,120），例如 模具和插入件彼此结合。 部件的接触焊盘（110C）中的一个包括金属，另一部件具有与金属反应形成金属硅化物（504）的硅（410）。 然后通过其中一个部件制成一个孔（510），以到达金属硅化物，甚至可能连接另一部件的未反应的金属（110C）。 该孔填充有可能是金属的导体（130），以提供可电耦合到可附接到其它电路元件或微电子部件的接触焊盘（120C.B）的导电通孔，例如。 到印刷电路板。