公开(公告)号：US10008469B2

公开(公告)日：2018-06-26

申请号：US15357553

申请日：2016-11-21

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Tu Tam Vu ,  Bongsub Lee ,  Kyong-Mo Bang ,  Xuan Li ,  Long Huynh ,  Gabriel Z. Guevara ,  Akash Agrawal ,  Willmar Subido ,  Laura Wills Mirkarimi

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L21/78 ,  H01L23/538 ,  H01L25/10 ,  H01L25/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L24/49 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/85 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/4801 ,  H01L2224/48235 ,  H01L2224/484 ,  H01L2224/4845 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/49177 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/85005 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/2064 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die. A portion of the plurality of wire bond wires extends outside a perimeter of the microelectronic die into a fan-out (“FO”) region. A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material.

公开(公告)号：US09928883B2

公开(公告)日：2018-03-27

申请号：US15595163

申请日：2017-05-15

Applicant: Invensas Corporation

Inventor： Zhuowen Sun ,  Kyong-Mo Bang ,  Belgacem Haba ,  Wael Zohni

IPC: G11C5/06 ,  G11C8/00 ,  G11C5/02 ,  H01L25/065 ,  G11C11/408

CPC classification number: G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C8/00 ,  G11C11/408 ,  H01L23/3128 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06136 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/1436 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/18165

Abstract: A microelectronic package can include a substrate having first and second surfaces, first, second, and third microelectronic elements each having a surface facing the first surface, terminals exposed at the second surface, and leads electrically connected between contacts of each microelectronic element and the terminals. The substrate can have first, second, and third spaced-apart apertures having first, second, and third parallel axes extending in directions of the lengths of the apertures. The contacts of the first, second, and third microelectronic elements can be aligned with one of the first, second, or third apertures. The terminals can include first and second sets of first terminals configured to carry address information. The first set can be connected with the first and third microelectronic elements and not with the second microelectronic element, and the second set can be connected with the second microelectronic element and not with the first or third microelectronic elements.

公开(公告)号：US09847238B2

公开(公告)日：2017-12-19

申请号：US15443371

申请日：2017-02-27

Applicant: Invensas Corporation

Inventor： Xuan Li ,  Rajesh Katkar ,  Long Huynh ,  Laura Wills Mirkarimi ,  Bongsub Lee ,  Gabriel Z. Guevara ,  Tu Tam Vu ,  Kyong-Mo Bang ,  Akash Agrawal

IPC: H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L25/00 ,  H01L21/02 ,  H01L23/00 ,  H01L21/304 ,  H01L23/29 ,  H01L25/065

CPC classification number: H01L21/568 ,  H01L21/02118 ,  H01L21/304 ,  H01L21/4846 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76838 ,  H01L21/76892 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/4985 ,  H01L23/5384 ,  H01L24/09 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/16111 ,  H01L2224/16237 ,  H01L2224/27436 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/73203 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/8185 ,  H01L2224/81903 ,  H01L2224/81904 ,  H01L2224/8192 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.

公开(公告)号：US20170323667A1

公开(公告)日：2017-11-09

申请号：US15595163

申请日：2017-05-15

Applicant: Invensas Corporation

Inventor： Zhuowen Sun ,  Kyong-Mo Bang ,  Belgacem Haba ,  Wael Zohni

IPC: G11C5/02 ,  H01L25/065 ,  G11C11/408 ,  G11C5/06 ,  G11C8/00

CPC classification number: G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C8/00 ,  G11C11/408 ,  H01L23/3128 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06136 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/1436 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/18165

Abstract: A microelectronic package can include a substrate having first and second surfaces, first, second, and third microelectronic elements each having a surface facing the first surface, terminals exposed at the second surface, and leads electrically connected between contacts of each microelectronic element and the terminals. The substrate can have first, second, and third spaced-apart apertures having first, second, and third parallel axes extending in directions of the lengths of the apertures. The contacts of the first, second, and third microelectronic elements can be aligned with one of the first, second, or third apertures. The terminals can include first and second sets of first terminals configured to carry address information. The first set can be connected with the first and third microelectronic elements and not with the second microelectronic element, and the second set can be connected with the second microelectronic element and not with the first or third microelectronic elements.

公开(公告)号：US20170294410A1

公开(公告)日：2017-10-12

申请号：US15095629

申请日：2016-04-11

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Kyong-Mo Bang

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: A microelectronic package includes at least one microelectronic element having a front surface defining a plane, the plane of each microelectronic element parallel to the plane of any other microelectronic element. An encapsulation region overlying edge surfaces of each microelectronic element has first and second major surfaces substantially parallel to the plane of each microelectronic element and peripheral surfaces between the major surfaces. Wire bonds are electrically coupled with one or more first package contacts at the first major surface of the encapsulation region, each wire bond having a portion contacted and surrounded by the encapsulation region. Second package contacts at an interconnect surface being one or more of the second major surface and the peripheral surfaces include portions of the wire bonds at such surface, and/or electrically conductive structure electrically coupled with the wire bonds.

公开(公告)号：US09679613B1

公开(公告)日：2017-06-13

申请号：US15148726

申请日：2016-05-06

Applicant: Invensas Corporation

Inventor： Zhuowen Sun ,  Kyong-Mo Bang ,  Belgacem Haba ,  Wael Zohni

IPC: G11C5/06 ,  G11C8/00 ,  G11C5/02 ,  H01L25/065 ,  G11C11/408

CPC classification number: G11C5/02 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C8/00 ,  G11C11/408 ,  H01L23/3128 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06136 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/1436 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/18165

Abstract: A microelectronic package can include a substrate having first and second surfaces, first, second, and third microelectronic elements each having a surface facing the first surface, terminals exposed at the second surface, and leads electrically connected between contacts of each microelectronic element and the terminals. The substrate can have first, second, and third spaced-apart apertures having first, second, and third parallel axes extending in directions of the lengths of the apertures. The contacts of the first, second, and third microelectronic elements can be aligned with one of the first, second, or third apertures. The terminals can include first and second sets of first terminals configured to carry address information. The first set can be connected with the first and third microelectronic elements and not with the second microelectronic element, and the second set can be connected with the second microelectronic element and not with the first or third microelectronic elements.

公开(公告)号：US20170103957A1

公开(公告)日：2017-04-13

申请号：US14877205

申请日：2015-10-07

Applicant: Invensas Corporation

Inventor： Xuan Li ,  Rajesh Katkar ,  Long Huynh ,  Laura Wills Mirkarimi ,  Bongsub Lee ,  Gabriel Z. Guevara ,  Tu Tam Vu ,  Kyong-Mo Bang ,  Akash Agrawal

IPC: H01L23/00 ,  H01L21/683 ,  H01L23/29 ,  H01L21/56 ,  H01L21/304 ,  H01L23/538 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L21/568 ,  H01L21/02118 ,  H01L21/304 ,  H01L21/4846 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76838 ,  H01L21/76892 ,  H01L23/293 ,  H01L23/3135 ,  H01L23/4985 ,  H01L23/5384 ,  H01L24/09 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/19 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/16111 ,  H01L2224/16237 ,  H01L2224/27436 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/73203 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/8185 ,  H01L2224/81903 ,  H01L2224/81904 ,  H01L2224/8192 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2924/0665 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Fan-out wafer-level packaging (WLP) using metal foil lamination is provided. An example wafer-level package incorporates a metal foil, such as copper (Cu), to relocate bonding pads in lieu of a conventional deposited or plated RDL. A polymer such as an epoxy layer adheres the metal foil to the package creating conductive contacts between the metal foil and metal pillars of a die. The metal foil may be patterned at different stages of a fabrication process. An example wafer-level package with metal foil provides relatively inexpensive electroplating-free traces that replace expensive RDL processes. Example techniques can reduce interfacial stress at fan-out areas to enhance package reliability, and enable smaller chips to be used. The metal foil provides improved fidelity of high frequency signals. The metal foil can be bonded to metallic pillar bumps before molding, resulting in less impact on the mold material.

公开(公告)号：US09349707B1

公开(公告)日：2016-05-24

申请号：US14609896

申请日：2015-01-30

Applicant: Invensas Corporation

Inventor： Zhuowen Sun ,  Yong Chen ,  Kyong-Mo Bang

IPC: H01L23/02 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L25/0652 ,  H01L21/486 ,  H01L23/13 ,  H01L23/34 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/17 ,  H01L24/43 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/16057 ,  H01L2224/16137 ,  H01L2224/16146 ,  H01L2224/16165 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/4502 ,  H01L2224/48138 ,  H01L2224/48148 ,  H01L2224/48165 ,  H01L2224/48235 ,  H01L2224/4824 ,  H01L2224/49174 ,  H01L2224/49177 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/1511 ,  H01L2924/152 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/3701 ,  H01L2224/45099

Abstract: An apparatus relates generally to a microelectronic assembly. In this apparatus, a first substrate and a second substrate each have opposing surfaces. Contact arrangements are disposed on a surface of the first substrate, including: first contacts disposed as a ring to provide a first array of the contact arrangements on such surface; and second contacts disposed interior to the ring of the first contacts to provide a second array of the contact arrangements on the first surface. The first contacts and the second contacts are for interconnection with first microelectronic dies and second microelectronic dies. The second microelectronic dies are disposed below the first microelectronic dies in same a package as the first microelectronic dies. The first microelectronic dies and the second microelectronic dies include at least two ranks thereof for commonly sharing the first contacts and the second contacts among the first microelectronic dies and the second microelectronic dies.

Abstract translation: 装置一般涉及微电子组件。 在该装置中，第一基板和第二基板各自具有相对的表面。 接触装置设置在第一基板的表面上，包括：作为环设置的第一触点，以在该表面上提供接触装置的第一阵列; 以及第二触点，其设置在第一触头的环的内部，以在第一表面上提供接触装置的第二阵列。 第一触点和第二触点用于与第一微电子管芯和第二微电子管芯互连。 第二微电子管芯以与第一微电子管芯相同的封装设置在第一微电子管芯的下方。 第一微电子管芯和第二微电子管芯包括至少两个等级，用于共同共享第一微触点和第一微电子管芯与第二微电子管芯之间的第二触点。

公开(公告)号：US09337170B1

公开(公告)日：2016-05-10

申请号：US14609878

申请日：2015-01-30

Applicant: Invensas Corporation

Inventor： Zhuowen Sun ,  Yong Chen ,  Kyong-Mo Bang

IPC: H01L29/40 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L25/0652 ,  H01L23/13 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An apparatus relates generally to a microelectronic assembly. In such an apparatus, a contact arrangements are disposed on a first surface of a first substrate, including first contacts disposed as a first ring array; second contacts disposed interior to the first contacts as a second ring array; third contacts disposed interior to the second contacts as a third ring array; and fourth contacts disposed interior to the third contacts on the first surface as an innermost array. The first ring array, the second ring array, and the third ring array are concentric rings with the innermost array in a central region of the concentric rings. The first contacts and the fourth contacts are for interconnection with first microelectronic dies. The second contacts and the third contacts are for interconnection with second microelectronic dies.

Abstract translation: 装置一般涉及微电子组件。 在这种装置中，接触装置设置在第一基板的第一表面上，包括设置为第一环阵列的第一触点; 第二触点设置在第一触点内部作为第二环阵列; 设置在第二触点内部的第三触点作为第三环阵列; 以及第四触点，其设置在第一表面上的作为最内侧阵列的第三触点的内部。 第一环阵列，第二环阵列和第三环阵列是在同心环的中心区域中具有最内阵列的同心环。 第一触点和第四触点用于与第一微电子模具互连。 第二触点和第三触点用于与第二微电子管芯互连。

公开(公告)号：US20150200183A1

公开(公告)日：2015-07-16

申请号：US14545019

申请日：2015-03-16

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Kyong-Mo Bang

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0655 ,  B81C1/00301 ,  H01L23/13 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/367 ,  H01L24/13 ,  H01L24/16 ,  H01L24/20 ,  H01L24/48 ,  H01L24/49 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/221 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48228 ,  H01L2224/4824 ,  H01L2224/49109 ,  H01L2224/4911 ,  H01L2224/96 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/19107 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A microelectronic assembly includes a first microelectronic package having a substrate with first and second opposed surfaces and substrate contacts thereon. The first package further includes first and second microelectronic elements, each having element contacts electrically connected with the substrate contacts and being spaced apart from one another on the first surface so as to provide an interconnect area of the first surface between the first and second microelectronic elements. A plurality of package terminals at the second surface are electrically interconnected with the substrate contacts for connecting the package with a component external thereto. A plurality of stack terminals are exposed at the first surface in the interconnect area for connecting the package with a component overlying the first surface of the substrate. The assembly further includes a second microelectronic package overlying the first microelectronic package and having terminals joined to the stack terminals of the first microelectronic package.

Abstract translation: 微电子组件包括具有其上具有第一和第二相对表面的衬底的衬底接触件的第一微电子封装。 第一封装进一步包括第一和第二微电子元件，每个微电子元件具有与基板触点电连接并且在第一表面上彼此间隔开的元件触点，以便在第一和第二微电子元件之间提供第一表面的互连区域 。 在第二表面处的多个封装端子与衬底触头电连接，用于将封装与外部的部件连接。 多个堆叠端子在互连区域中的第一表面处露出，用于将封装件与覆盖在基板的第一表面上的部件连接。 组件还包括覆盖第一微电子封装并具有连接到第一微电子封装的堆叠端子的端子的第二微电子封装。