公开(公告)号：US07524731B2

公开(公告)日：2009-04-28

申请号：US11540614

申请日：2006-09-29

Applicant: James Jen-Ho Wang

Inventor： James Jen-Ho Wang

IPC: H01L21/20

CPC classification number: H01L23/5227 ,  H01F17/0033 ,  H01F2027/2814 ,  H01L23/552 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/092 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/4845 ,  H01L2224/48455 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01014 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/20752 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: An electronic device can include an inductor overlying a shock-absorbing layer. In one aspect, the electronic device can include a substrate, an interconnect level overlying the substrate, and the shock-absorbing layer overlying the interconnect level. The inductor can include conductive traces and looped wires. The conductive traces can be attached to the conductive traces over the shock-absorbing layer. In another aspect, a process can be used to form the electronic device including the inductor. In still another aspect, an electronic device can a toroidal-shaped inductor that includes linear inductor segments that are connected in series.

Abstract translation: 电子设备可以包括覆盖减震层的电感器。 在一个方面，电子设备可以包括衬底，覆盖衬底的互连电平以及覆盖互连电平的减震层。 电感器可以包括导电迹线和环形导线。 导电迹线可以连接到震动吸收层上的导电迹线上。 在另一方面，可以使用一种方法来形成包括电感器的电子设备。 另一方面，电子设备可以是包括串联连接的线性电感器段的环形电感器。

公开(公告)号：US20080079115A1

公开(公告)日：2008-04-03

申请号：US11540614

申请日：2006-09-29

Applicant: James Jen-Ho Wang

Inventor： James Jen-Ho Wang

IPC: H01L29/00 ,  H01L21/8222

CPC classification number: H01L23/5227 ,  H01F17/0033 ,  H01F2027/2814 ,  H01L23/552 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L27/092 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/4845 ,  H01L2224/48455 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/49175 ,  H01L2224/49431 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01014 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/20752 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: An electronic device can include an inductor overlying a shock-absorbing layer. In one aspect, the electronic device can include a substrate, an interconnect level overlying the substrate, and the shock-absorbing layer overlying the interconnect level. The inductor can include conductive traces and looped wires. The conductive traces can be attached to the conductive traces over the shock-absorbing layer. In another aspect, a process can be used to form the electronic device including the inductor. In still another aspect, an electronic device can a toroidal-shaped inductor that includes linear inductor segments that are connected in series.

Abstract translation: 电子设备可以包括覆盖减震层的电感器。 在一个方面，电子设备可以包括衬底，覆盖衬底的互连电平以及覆盖互连电平的减震层。 电感器可以包括导电迹线和环形导线。 导电迹线可以连接到震动吸收层上的导电迹线上。 在另一方面，可以使用一种方法来形成包括电感器的电子设备。 另一方面，电子设备可以是包括串联连接的线性电感器段的环形电感器。

公开(公告)号：US06888246B2

公开(公告)日：2005-05-03

申请号：US10447457

申请日：2003-05-29

Applicant: Lei L. Mercado ,  Vijay Sarihan ,  Young Sir Chung ,  James Jen-Ho Wang ,  Edward R. Prack

Inventor： Lei L. Mercado ,  Vijay Sarihan ,  Young Sir Chung ,  James Jen-Ho Wang ,  Edward R. Prack

IPC: H01L21/60 ,  H01L21/768 ,  H01L23/31 ,  H01L23/485 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52

CPC classification number: H01L24/12 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/5329 ,  H01L24/05 ,  H01L24/11 ,  H01L24/48 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05082 ,  H01L2224/05599 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05618 ,  H01L2224/05623 ,  H01L2224/05644 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/0567 ,  H01L2224/05671 ,  H01L2224/05679 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/1411 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/85207 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01039 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2924/00

Abstract: In accordance with one embodiment, a stress buffer (40) is formed between a power metal structure (90) and passivation layer (30). The stress buffer (40) reduces the effects of stress imparted upon the passivation layer (30) by the power metal structure (90). In accordance with an alternative embodiment, a power metal structure (130A) is partitioned into segments (1091), whereby electrical continuity is maintained between the segments (1090) by remaining portions of a seed layer (1052) and adhesion/barrier layer (1050). The individual segments (1090) impart a lower peak stress than a comparably sized continuous power metal structure (9).

Abstract translation: 根据一个实施例，在功率金属结构（90）和钝化层（30）之间形成应力缓冲器（40）。 应力缓冲器（40）减少由功率金属结构（90）施加在钝化层（30）上的应力的影响。 根据替代实施例，功率金属结构（130A）被分割成段（1091），由此通过种子层（1052）和粘附/阻挡层（1052）的剩余部分在段（1090）之间保持电连续性 1050）。 单个段（1090）赋予比相对大小的连续功率金属结构（9）更低的峰值应力。

公开(公告)号：US6001493A

公开(公告)日：1999-12-14

申请号：US88026

申请日：1998-06-01

Applicant: James L. Rutledge ,  Kenneth Kaskoun ,  James Jen-Ho Wang

Inventor： James L. Rutledge ,  Kenneth Kaskoun ,  James Jen-Ho Wang

IPC: H01L21/60 ,  H01L23/485 ,  H05K3/34 ,  H01L29/12

CPC classification number: H01L24/13 ,  H01L24/11 ,  H05K3/3473 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K2201/10674 ,  H05K2203/0338 ,  H05K2203/0726 ,  H05K2203/1476 ,  Y10T156/1089 ,  Y10T428/12417 ,  Y10T428/12486 ,  Y10T428/12528 ,  Y10T428/12597 ,  Y10T428/21 ,  Y10T428/23921 ,  Y10T428/2933

Abstract: A first pattern of bumps and a second pattern of bumps are formed on a substrate (10) with bumps (14,15). During a transfer process, only the bumps (14) of the first pattern of bumps are transferred to pad extensions (20) of a device (17). The bumps (15) of the second pattern of bumps are not affected by this process and can be later transferred to a second device.

Abstract translation: 在具有凸块（14,15）的基板（10）上形成凸起的第一图案和第二凸起图案。 在转移过程中，只有凸起的第一图案的凸块（14）被转移到装置（17）的焊盘延伸部（20）上。 凸起的第二图案的凸起（15）不受该处理的影响，并且可以稍后传送到第二装置。

公开(公告)号：US20170186533A9

公开(公告)日：2017-06-29

申请号：US14531079

申请日：2014-11-03

Applicant: James Jen-Ho Wang

Inventor： James Jen-Ho Wang

IPC: H01F41/02 ,  H05K1/18 ,  H05B33/08

CPC classification number: H01F41/0206 ,  H01F17/0013 ,  H01F41/046 ,  H01F2017/006 ,  H01F2017/0066 ,  H05B33/0803 ,  H05B33/0821 ,  H05B33/0845 ,  H05K1/0209 ,  H05K1/021 ,  H05K1/0271 ,  H05K1/028 ,  H05K1/0283 ,  H05K1/165 ,  H05K1/183 ,  H05K1/189 ,  H05K3/0005 ,  H05K3/0035 ,  H05K3/0061 ,  H05K3/0097 ,  H05K3/281 ,  H05K3/427 ,  H05K3/4697 ,  H05K2201/056 ,  H05K2201/086 ,  H05K2201/0919 ,  H05K2201/09672 ,  H05K2201/09709 ,  H05K2201/09845 ,  H05K2203/0126 ,  H05K2203/0384 ,  H05K2203/0571 ,  H05K2203/063 ,  H05K2203/1545

Abstract: An embedded device 105 is assembled within a flexible circuit assembly 30 with the embedded device mid-plane intentionally located in proximity to the flexible circuit assembly central plane 115 to minimize stress effects on the embedded device. The opening 18, for the embedded device, is enlarged in an intermediate layer 10 to enhance flexibility of the flexible circuit assembly.

公开(公告)号：USD732731S1

公开(公告)日：2015-06-23

申请号：US29421678

申请日：2012-09-04

Applicant: James Jen-Ho Wang

Designer： James Jen-Ho Wang

公开(公告)号：US08153510B2

公开(公告)日：2012-04-10

申请号：US12799444

申请日：2010-04-26

Applicant: James Jen-Ho Wang

Inventor： James Jen-Ho Wang

IPC: H01L21/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4813 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/05442 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2924/207

Abstract: In a semiconductor wafer, the polyimide film underneath a power metal structure is partially etched to create corresponding surface depressions of the conformal top power metal. The depressions at the surface of power metal are visible under optical microscopy. Arrangement of the depressions in a pattern facilitates the alignment of probe needles, set-up of automated wire bonding and microscopic inspection for precise alignment of wire bonds.

Abstract translation: 在半导体晶片中，功率金属结构下方的聚酰亚胺膜被部分蚀刻，以产生适形顶部功率金属的相应的表面凹陷。 功率金属表面的凹陷在光学显微镜下是可见的。 以图案排列凹陷有助于探针的对准，自动引线接合的设置和显微检查以精确对准引线接合。

公开(公告)号：US07868729B2

公开(公告)日：2011-01-11

申请号：US12397112

申请日：2009-03-03

Applicant: James Jen-Ho Wang ,  Carl E. D'Acosta ,  Justin E. Poarch

Inventor： James Jen-Ho Wang ,  Carl E. D'Acosta ,  Justin E. Poarch

IPC: H01F5/00

CPC classification number: H01F17/0013 ,  H01F17/04 ,  H01F27/2804 ,  H01F2017/002 ,  H01F2027/2814 ,  H01L23/645 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81012 ,  H01L2224/81013 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2225/06527 ,  H01L2225/06586 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/07802 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  Y10T29/4902 ,  Y10T29/49117 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A stacked semiconductor device assembly (20) includes a device (24) having conductive traces (34) formed therein, and conductive interconnects (28) electrically connected to the conductive traces (34). Another device (26) has conductive traces (44) formed therein and device pads (54) formed on an outer surface (52) of the device (26). A method (120) entails attaching (84) a magnetic core (30) to an outer surface (42) of the device (24) and forming (92) the conductive interconnects (28) on the outer surface (42) using a stud bumping technique such that the interconnects (28) surround the magnetic core (30). The conductive interconnects (28) are coupled (126) with the device pads (54) using thermocompression bonding to couple the device (26) with the device (24) to form a continuous device coil (22) wrapped around the magnetic core (30) from an alternating electrical connection of the traces (34), the conductive interconnects (28), and the traces (44).

Abstract translation: 层叠的半导体器件组件（20）包括其中形成有导电迹线（34）的器件（24）和电连接到导电迹线（34）的导电互连（28）。 另一个装置（26）具有形成在其中的导电迹线（44）和形成在装置（26）的外表面（52）上的装置焊盘（54）。 方法（120）需要将磁芯（84）附接到装置（24）的外表面（42）上，并且使用螺柱（92）在外表面（42）上形成（92）导电互连件（28） 使得互连（28）围绕磁芯（30）的凸起技术。 使用热压接将导电互连（28）与器件焊盘（54）耦合（126），以将器件（26）与器件（24）耦合以形成围绕磁芯（30）缠绕的连续器件线圈（22） ）从导线（34），导电互连（28）和迹线（44）的交替电连接。

公开(公告)号：US20100279489A1

公开(公告)日：2010-11-04

申请号：US12799444

申请日：2010-04-26

Applicant: James Jen-Ho Wang

Inventor： James Jen-Ho Wang

IPC: H01L21/768 ,  H01L21/78 ,  H01B13/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/04042 ,  H01L2224/05073 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4813 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/05442 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00014 ,  H01L2224/48824 ,  H01L2924/00 ,  H01L2924/207

Abstract: In a semiconductor wafer, the polyimide film underneath a power metal structure is partially etched to create corresponding surface depressions of the conformal top power metal. The depressions at the surface of power metal are visible under optical microscopy. Arrangement of the depressions in a pattern facilitates the alignment of probe needles, set-up of automated wire bonding and microscopic inspection for precise alignment of wire bonds.

Abstract translation: 在半导体晶片中，功率金属结构下方的聚酰亚胺膜被部分蚀刻，以产生适形顶部功率金属的相应的表面凹陷。 功率金属表面的凹陷在光学显微镜下是可见的。 以图案排列凹陷有助于探针的对准，自动引线接合的设置和显微检查以精确对准引线接合。

公开(公告)号：US20100225434A1

公开(公告)日：2010-09-09

申请号：US12397112

申请日：2009-03-03

Applicant: James Jen-Ho Wang ,  Carl E. D'Acosta ,  Justin E. Poarch

Inventor： James Jen-Ho Wang ,  Carl E. D'Acosta ,  Justin E. Poarch

IPC: H01F5/00 ,  H01R43/00

CPC classification number: H01F17/0013 ,  H01F17/04 ,  H01F27/2804 ,  H01F2017/002 ,  H01F2027/2814 ,  H01L23/645 ,  H01L24/11 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81012 ,  H01L2224/81013 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2225/06527 ,  H01L2225/06586 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/07802 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104 ,  Y10T29/4902 ,  Y10T29/49117 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A stacked semiconductor device assembly (20) includes a device (24) having conductive traces (34) formed therein, and conductive interconnects (28) electrically connected to the conductive traces (34). Another device (26) has conductive traces (44) formed therein and device pads (54) formed on an outer surface (52) of the device (26). A method (120) entails attaching (84) a magnetic core (30) to an outer surface (42) of the device (24) and forming (92) the conductive interconnects (28) on the outer surface (42) using a stud bumping technique such that the interconnects (28) surround the magnetic core (30). The conductive interconnects (28) are coupled (126) with the device pads (54) using thermocompression bonding to couple the device (26) with the device (24) to form a continuous device coil (22) wrapped around the magnetic core (30) from an alternating electrical connection of the traces (34), the conductive interconnects (28), and the traces (44).

Abstract translation: 层叠的半导体器件组件（20）包括其中形成有导电迹线（34）的器件（24）和电连接到导电迹线（34）的导电互连（28）。 另一个装置（26）具有形成在其中的导电迹线（44）和形成在装置（26）的外表面（52）上的装置焊盘（54）。 方法（120）需要将磁芯（84）附接到装置（24）的外表面（42）上，并且使用螺柱（92）在外表面（42）上形成（92）导电互连件（28） 使得互连（28）围绕磁芯（30）的凸起技术。 使用热压接将导电互连（28）与器件焊盘（54）耦合（126），以将器件（26）与器件（24）耦合以形成围绕磁芯（30）缠绕的连续器件线圈（22） ）从导线（34），导电互连（28）和迹线（44）的交替电连接。