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    Memory Cells and Methods of Forming a Capacitor
    21.
    发明申请
    Memory Cells and Methods of Forming a Capacitor 审中-公开

    公开(公告)号：US20180197870A1

    公开(公告)日：2018-07-12

    申请号：US15404576

    申请日：2017-01-12

    Applicant: Micron Technology, Inc.

    Inventor： Muralikrishnan Balakrishnan ,  Beth R. Cook ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01L27/11509 ,  H01L49/02

    CPC classification number: H01L28/65 ,  H01L27/11507 ,  H01L28/75 ,  H01L28/91

    Abstract: A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode. The parallel current leakage path is circuit-parallel the intrinsic current leakage path and of lower total resistance than the intrinsic current leakage path. Other aspects, including methods, are disclosed.

    Memory cells comprising ferroelectric material and including current leakage paths having different total resistances
    26.
    发明授权
    Memory cells comprising ferroelectric material and including current leakage paths having different total resistances 有权

    公开(公告)号：US11600691B2

    公开(公告)日：2023-03-07

    申请号：US17125030

    申请日：2020-12-17

    Applicant: Micron Technology, Inc.

    Inventor： Muralikrishnan Balakrishnan ,  Beth R. Cook ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01L49/02 ,  H01L27/11507

    Abstract: A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode. The parallel current leakage path is circuit-parallel the intrinsic current leakage path and of lower total resistance than the intrinsic current leakage path. Other aspects, including methods, are disclosed.

    Ferroelectric Devices and Methods of Forming Ferroelectric Devices
    28.
    发明申请
    Ferroelectric Devices and Methods of Forming Ferroelectric Devices 审中-公开

    公开(公告)号：US20200227423A1

    公开(公告)日：2020-07-16

    申请号：US16834666

    申请日：2020-03-30

    Applicant: Micron Technology, Inc.

    Inventor： Ashonita A. Chavan ,  Ramanathan Gandhi ,  Beth R. Cook ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01L27/11507 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L27/1159 ,  H01L49/02

    Abstract: Some embodiments include a ferroelectric device comprising ferroelectric material adjacent an electrode. The device includes a semiconductor material-containing region along a surface of the ferroelectric material nearest the electrode. The semiconductor material-containing region has a higher concentration of semiconductor material than a remainder of the ferroelectric material. The device may be, for example, a transistor or a capacitor. The device may be incorporated into a memory array. Some embodiments include a method of forming a ferroelectric capacitor. An oxide-containing ferroelectric material is formed over a first electrode. A second electrode is formed over the oxide-containing ferroelectric material. A semiconductor material-enriched portion of the oxide-containing ferroelectric material is formed adjacent the second electrode.

    Methods of forming a capacitor comprising ferroelectric material and including current leakage paths having different total resistances
    29.
    发明授权
    Methods of forming a capacitor comprising ferroelectric material and including current leakage paths having different total resistances 有权

    公开(公告)号：US10680057B2

    公开(公告)日：2020-06-09

    申请号：US16527301

    申请日：2019-07-31

    Applicant: Micron Technology, Inc.

    Inventor： Muralikrishnan Balakrishnan ,  Beth R. Cook ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01L27/11507 ,  H01L49/02

    Abstract: A memory cell comprises a capacitor having a first conductive capacitor electrode having laterally-spaced walls that individually have a top surface. A second conductive capacitor electrode is laterally between the walls of the first capacitor electrode, and comprises a portion above the first capacitor electrode. Ferroelectric material is laterally between the walls of the first capacitor electrode and laterally between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the ferroelectric material. A parallel current leakage path is between an elevationally-inner surface of the portion of the second capacitor electrode that is above the first capacitor electrode and at least one of the individual top surfaces of the laterally-spaced walls of the first capacitor electrode. The parallel current leakage path is circuit-parallel the intrinsic current leakage path and of lower total resistance than the intrinsic current leakage path. Other aspects, including methods, are disclosed.

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