公开(公告)号：US12046658B2

公开(公告)日：2024-07-23

申请号：US16509204

申请日：2019-07-11

Applicant: Micron Technology, Inc.

Inventor： An-Jen B. Cheng ,  Brenda D. Kraus ,  Sanket S. Kelkar ,  Matthew N. Rocklein ,  Christopher W. Petz ,  Richard Beeler ,  Dojun Kim

IPC: H01G4/018 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H10B12/00 ,  H01G4/005

CPC classification number: H01L29/517 ,  H01G4/018 ,  H01L21/02156 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/28194 ,  H10B12/30 ,  H01G4/005 ,  H01L21/02164 ,  H01L21/02194

Abstract: Apparatuses, methods, and systems related to electrode formation are described. A first portion of a top electrode is formed over a dielectric material of a storage node. A metal oxide is formed over the first portion of the electrode. A second portion of the electrode is formed over the metal oxide.

公开(公告)号：US11417661B2

公开(公告)日：2022-08-16

申请号：US16805802

申请日：2020-03-01

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Matthew N. Rocklein ,  Brett W. Busch

IPC: H01L27/108 ,  H01L49/02

Abstract: Some embodiments include an integrated capacitor assembly having a conductive pillar supported by a base, with the conductive pillar being included within a first electrode of a capacitor. The conductive pillar has a first upper surface. A dielectric liner is along an outer surface of the conductive pillar and has a second upper surface. A conductive liner is along the dielectric liner and is included within a second electrode of the capacitor. The conductive liner has a third upper surface. One of the first and third upper surfaces is above the other of the first and third upper surfaces. The second upper surface is at least as high above the base as said one of the first and third upper surfaces. Some embodiments include memory arrays having capacitors with pillar-type first electrodes.

公开(公告)号：US20220238532A1

公开(公告)日：2022-07-28

申请号：US17647902

申请日：2022-01-13

Applicant: Micron Technology, Inc.

Inventor： Devesh Dadhich Shreeram ,  Kangle Li ,  Matthew N. Rocklein ,  Wei Ching Huang ,  Ping-Cheng Hsu ,  Sevim Korkmaz ,  Sanjeev Sapra ,  An-Jen B. Cheng

IPC: H01L27/108

Abstract: A DRAM capacitor may include a first capacitor electrode, a capacitor dielectric adjacent to the first capacitor electrode, and a second capacitor electrode adjacent to the capacitor dielectric. The first capacitor electrode may include a lower portion, an upper portion, and a step transition between the lower portion and the upper portion, a width of the upper portion of the first capacitor electrode at the step transition is less than a width of the lower portion of the first capacitor electrode at the step transition. Semiconductor devices, systems, and methods are also disclosed.

公开(公告)号：US20220208767A1

公开(公告)日：2022-06-30

申请号：US17655257

申请日：2022-03-17

Applicant: Micron Technology, Inc.

Inventor： Matthew N. Rocklein ,  Paul A. Paduano ,  Sanket S. Kelkar ,  Christopher W. Petz ,  Zhe Song ,  Vassil Antonov ,  Qian Tao

IPC: H01L27/108 ,  H01L21/285 ,  H01L49/02

Abstract: A DRAM capacitor comprising a first capacitor electrode configured as a container and comprising a doped titanium nitride material, a capacitor dielectric on the first capacitor electrode, and a second capacitor electrode on the capacitor dielectric. Methods of forming the DRAM capacitor are also disclosed, as are semiconductor devices and systems comprising such DRAM capacitors.

公开(公告)号：US11139256B2

公开(公告)日：2021-10-05

申请号：US16547289

申请日：2019-08-21

Applicant: Micron Technology, Inc.

Inventor： Diana C. Majerus ,  Scott D. Van De Graaff ,  Matthew N. Rocklein

IPC: H01L23/00

Abstract: Systems, apparatus, and methods related to tamper-resistant integrated circuits are described. The tamper-resistant integrated circuits include tamper-resistant features including a tamper-resistant material formulated or configured to exhibit a change in at least one electrical property responsive to exposure to oxygen, electromagnetic radiation, or other environmental conditions. Data located within the integrated circuit may be erased, or at least a portion of the integrated circuit may be destroyed, responsive to a change in the at least one electrical property. In some examples, one or more electrical properties of a tamper-resistant feature may be measured. A change in an electrical property may be an indication that the associated integrated circuit has been tampered with.

公开(公告)号：US20210050409A1

公开(公告)日：2021-02-18

申请号：US16543065

申请日：2019-08-16

Applicant: Micron Technology, Inc.

Inventor： Matthew N. Rocklein ,  An-Jen B. Cheng ,  Fredrick D. Fishburn ,  Sevim Korkmaz ,  Paul A. Paduano

IPC: H01L49/02 ,  H01L21/285 ,  H01L21/02 ,  H01L21/311

Abstract: Methods, apparatuses, and systems related to trim a semiconductor structure using oxygen are described. An example method includes forming a support structure for a semiconductor structure having a first silicate material on a working surface. The method further includes forming a first nitride material on the first silicate material. The method further includes forming a second silicate material on the first nitride material. The method further includes forming a second nitride material on the second silicate material. The method further includes forming an opening through the semiconductor structure. The method further includes depositing an electrode material within the opening. The method further includes removing portions of the support structure. The method further includes performing a controlled oxidative trim to an upper portion of the electrode material.

公开(公告)号：US10586923B2

公开(公告)日：2020-03-10

申请号：US15662974

申请日：2017-07-28

Applicant: Micron Technology, Inc.

Inventor： Matthew N. Rocklein ,  D. V. Nirmal Ramaswamy

IPC: H01L45/00 ,  H01L27/24

Abstract: Semiconductor memory devices, resistive memory devices, memory cell structures, and methods of forming a resistive memory cell are provided. One example method of a resistive memory cell can include a number of dielectric regions formed between two electrodes, and a barrier dielectric region formed between each of the dielectric regions. The barrier dielectric region serves to reduce an oxygen diffusion rate associated with the dielectric regions.

公开(公告)号：US10438643B2

公开(公告)日：2019-10-08

申请号：US16194820

申请日：2018-11-19

Applicant: Micron Technology, Inc.

Inventor： Steven C. Nicholes ,  Ashonita A. Chavan ,  Matthew N. Rocklein

IPC: G11C11/00 ,  G11C11/22 ,  H01L27/11502 ,  G11C14/00 ,  G11C11/56 ,  G11C13/04 ,  H01L27/11507 ,  H01L49/02

Abstract: Methods of operating a ferroelectric memory cell. The method includes applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell having a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. Another of the positive bias voltage and the negative bias voltage is applied to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from an absolute value of the positive bias voltage. Related ferroelectric memory cells include a ferroelectric material exhibiting asymmetric switching properties.

公开(公告)号：US10177152B1

公开(公告)日：2019-01-08

申请号：US15656999

申请日：2017-07-21

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Matthew N. Rocklein ,  Brett W. Busch

IPC: H01L27/108 ,  H01L49/02

Abstract: Some embodiments include an integrated capacitor assembly having a conductive pillar supported by a base, with the conductive pillar being included within a first electrode of a capacitor. The conductive pillar has a first upper surface. A dielectric liner is along an outer surface of the conductive pillar and has a second upper surface. A conductive liner is along the dielectric liner and is included within a second electrode of the capacitor. The conductive liner has a third upper surface. One of the first and third upper surfaces is above the other of the first and third upper surfaces. The second upper surface is at least as high above the base as said one of the first and third upper surfaces. Some embodiments include memory arrays having capacitors with pillar-type first electrodes.

公开(公告)号：US09698343B2

公开(公告)日：2017-07-04

申请号：US14936013

申请日：2015-11-09

Applicant: Micron Technology, Inc.

Inventor： Qian Tao ,  Matthew N. Rocklein ,  Beth R. Cook ,  D.V. Nirmal Ramaswamy

IPC: H01L47/00 ,  H01L45/00 ,  H01L27/11507 ,  H01L49/02

CPC classification number: H01L27/11507 ,  H01L28/60 ,  H01L45/04 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1641

Abstract: A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.