公开(公告)号：US20210019051A1

公开(公告)日：2021-01-21

申请号：US16916922

申请日：2020-06-30

Applicant: Micron Technology, Inc.

Inventor： Fangfang Zhu ,  Jiangli Zhu ,  Ying Yu Tai ,  Wei Wang

IPC: G06F3/06

Abstract: Methods, systems, and devices for one or more acceleration engines for memory sub-system operations are described. An acceleration engine can receive a first command for performing an operation on a set of management units. The acceleration engine can generate a set of one or more second commands to perform the operation on each management unit of the set of management units based on receiving the first command. The acceleration engine can perform the operation on each management unit of the set of management units based on generating the set of second commands.

公开(公告)号：US20200278808A1

公开(公告)日：2020-09-03

申请号：US16289053

申请日：2019-02-28

Applicant: Micron Technology, Inc.

Inventor： Jiangli Zhu ,  Wei Wang ,  Ying Yu Tai ,  Jason Duong ,  Chih-Kuo Kao

IPC: G06F3/06

Abstract: A processing device in a memory system provides an execution grant to a first queue of a plurality of queues, the first queue storing a first plurality of memory commands to be executed on the memory component. The processing device further determines whether a number of commands from the first queue that have been executed since the first queue received the execution grant satisfies an executed transaction threshold criterion and whether a number of pending commands in a second queue of the plurality of queues satisfies a promotion threshold criterion, the second queue storing a second plurality of memory commands to be executed on the memory component. Responsive to at least one of the executed transaction threshold criterion or the promotion threshold criterion being satisfied, the processing device provides the execution grant to the second queue.

公开(公告)号：US20240419543A1

公开(公告)日：2024-12-19

申请号：US18821484

申请日：2024-08-30

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung Lien ,  Zhenming Zhou ,  Wei Wang

IPC: G06F11/10 ,  G06F11/14 ,  G06F11/34

Abstract: A method includes generating parity data corresponding to a plurality of word lines coupled to blocks of a memory device and generating additional parity data for a block based on a physical location of the block. The method can further include performing a data recovery operation based on the parity data, the additional parity data, or a combination thereof.

公开(公告)号：US20240377990A1

公开(公告)日：2024-11-14

申请号：US18673228

申请日：2024-05-23

Applicant: Micron Technology, Inc.

Inventor： Fangfang Zhu ,  Jiangli Zhu ,  Ying Tai ,  Wei Wang

IPC: G06F3/06 ,  G06F11/10

Abstract: Methods, systems, and devices for one or more acceleration engines for memory sub-system operations are described. An acceleration engine can perform one or more validation procedures on one or more codewords of a management unit. The acceleration engine can collect validation data for the management unit based on performing the validation procedures. The acceleration engine can aggregate the validation data into group validation data associated with a set of management units. The acceleration engine can transmit the group validation data to firmware of a memory sub-system or a host device.

公开(公告)号：US20240330717A1

公开(公告)日：2024-10-03

申请号：US18597851

申请日：2024-03-06

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung Lien ,  Wei Wang ,  Zhenming Zhou

IPC: G06N5/022 ,  G06F12/02

CPC classification number: G06N5/022 ,  G06F12/0246

Abstract: A method for using and system for training a trainable model to predict values of memory configuration parameters based on a value of a performance metric. The value of the performance metric is based on a threshold condition of a memory access operation performed on a memory device using a set of values of the memory configuration parameters. The output of the trainable model includes a set of predicted values of the memory configuration parameters. Responsive to determining that the set of predicted values of the memory configuration parameters satisfies a confidence criterion, the memory configuration parameters are updated to reflect the set of predicted values of the memory configuration parameters.

公开(公告)号：US12026042B2

公开(公告)日：2024-07-02

申请号：US17858731

申请日：2022-07-06

Applicant: Micron Technology, Inc.

Inventor： Charles See Yeung Kwong ,  Seungjune Jeon ,  Wei Wang ,  Zhenming Zhou

IPC: G06F11/00 ,  G06F11/07

CPC classification number: G06F11/076 ,  G06F11/008 ,  G06F11/073 ,  G06F2201/81 ,  G06F2212/7211

Abstract: A set of blocks of a memory device comprising a plurality of dies is identified. A block within the set of blocks is identified. The identified block is associated with a capability metric that reflects a projected reliability of the die on which the block resides. Responsive to determining that the capability metric satisfies a condition, a cycle threshold associated with the die is identified. Responsive to determining that a cycle count value derived from a program/erase cycle counter associated with the die matches the cycle threshold, the set of blocks is updated by excluding the block from the set of blocks. A program operation is performed with respect to the updated set of blocks.

公开(公告)号：US20240104030A1

公开(公告)日：2024-03-28

申请号：US18531642

申请日：2023-12-06

Applicant: Micron Technology, Inc.

Inventor： Wei Wang ,  Jiangli Zhu ,  Ying Yu Tai ,  Samir Mittal

IPC: G06F13/16 ,  G06F3/06 ,  G11C7/10

CPC classification number: G06F13/1642 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0671 ,  G11C7/1045 ,  G06F2213/16

Abstract: A data bus coupled to a plurality of memory devices is determined to be in a read mode. Responsive to determining that the data bus is in the read mode, a particular read operation identified in a particular memory queue of memory queues that include identifiers of one or more write operations and identifiers of one or more read operations is determined. The particular memory queue includes a highest number of read operations for a memory device of the memory devices. The particular read operation is transmitted from the particular memory queue over the data bus.

公开(公告)号：US20240062839A1

公开(公告)日：2024-02-22

申请号：US17892437

申请日：2022-08-22

Applicant: Micron Technology, Inc.

Inventor： Wei Wang ,  Seungjune Jeon ,  Yang Liu ,  Charles See Yeung Kwong

IPC: G11C16/34 ,  G11C16/04

CPC classification number: G11C16/3431 ,  G11C16/0483

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a data integrity check on a set of memory cells of a source management unit of the memory device to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a first threshold; responsive to determining that the data integrity metric value fails to satisfy the first threshold, determining whether the data integrity metric value satisfies a second threshold that is lower than the first threshold; responsive to determining that the data integrity metric value satisfies the second threshold, causing the memory device to copy data from the source management unit to a destination set of pages of the memory device; and performing a subsequent data integrity check on one or more invalid pages of the source management unit.

公开(公告)号：US11782606B2

公开(公告)日：2023-10-10

申请号：US17730958

申请日：2022-04-27

Applicant: Micron Technology, Inc.

Inventor： Fangfang Zhu ,  Wei Wang ,  Jiangli Zhu ,  Ying Yu Tai

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673

Abstract: Methods, systems, and devices for memory can include techniques for identifying first quantities of write counts for a first plurality of super management units (SMUs) in a mapped region of a memory sub-system, identifying, by a hardware component of the memory sub-system, a first SMU of the first plurality that includes a fewest quantity of write counts of the first quantity of write counts, and performing a wear-leveling operation based at least in part on a first quantity of write counts of the first SMU of the first plurality in the mapped region being less than a second quantity of writes counts of a second SMU of a second plurality of SMUs in an unmapped region of the memory sub-system.

公开(公告)号：US20230207042A1

公开(公告)日：2023-06-29

申请号：US18117599

申请日：2023-03-06

Applicant: Micron Technology, Inc.

Inventor： Venkata Naga Lakshman Pasala ,  Wei Wang ,  Jiangli Zhu

IPC: G11C29/42 ,  G11C29/40 ,  G11C7/02 ,  G11C29/44

CPC classification number: G11C29/42 ,  G11C29/40 ,  G11C7/02 ,  G11C29/4401 ,  G11C2029/1208

Abstract: A system includes a plurality of memory dice and a processing device coupled to the plurality of memory dice. The processing device is to determine whether an error correcting code (ECC) check of ECC-protected data read from a die of the plurality of memory dice results in detecting an error. In response to detecting the error from the ECC-protected data, the processing device performs a confirmation check that the error is a result of a defect in the die. In response to the confirmation check confirming the die is defective, the processing device ignores a temperature value from the die when determining whether to trigger a thermal-related operation.