公开(公告)号：US20160284789A1

公开(公告)日：2016-09-29

申请号：US15178900

申请日：2016-06-10

Applicant: QUALCOMM Incorporated

Inventor： Chengjie ZUO ,  Jonghae KIM ,  Daeik Daniel KIM ,  Changhan Hobie YUN ,  Mario Francisco VELEZ

IPC: H01L49/02 ,  H01F27/28 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00

Abstract: Base pads are spaced by a pitch on a support surface. Conducting members, optionally Cu or other metal pillars, extend up from the base pads to top pads. A top pad interconnector connects the top pads in a configuration establishing an inductor current path between the base pads.

公开(公告)号：US20160276101A1

公开(公告)日：2016-09-22

申请号：US15167782

申请日：2016-05-27

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  Jonghae KIM ,  Chengjie ZUO ,  Mario Francisco VELEZ ,  Changhan Hobie YUN

IPC: H01F41/04

CPC classification number: H01F41/041 ,  H01F27/2804 ,  H01F41/00 ,  H01F2017/0086 ,  H01F2027/2809 ,  H01L2924/0002 ,  Y10T29/4902 ,  H01L2924/00

Abstract: A 3D nested transformer includes a substrate having a set of through substrate vias daisy chained together with a set of traces. At least some of the through substrate vias have first and second conductive regions. The set of traces also includes a first set of traces coupling together at least some of the first conductive regions of the through substrate vias, and a second set of traces coupling together at least some of the second conductive regions of the through substrate vias.

公开(公告)号：US20150279920A1

公开(公告)日：2015-10-01

申请号：US14229317

申请日：2014-03-28

Applicant: QUALCOMM INCORPORATED

Inventor： Chengjie ZUO ,  Jonghae KIM ,  Daeik Daniel KIM ,  Changhan Hobie YUN ,  Mario Francisco VELEZ

IPC: H01L49/02 ,  H01L21/48

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F27/2804 ,  H01F2017/002 ,  H01L21/486 ,  H01L21/4889 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L24/17 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/19011 ,  H01L2924/19042 ,  H01L2924/19102

Abstract: Base pads are spaced by a pitch on a support surface. Conducting members, optionally Cu or other metal pillars, extend up from the base pads to top pads. A top pad interconnector connects the top pads in a configuration establishing an inductor current path between the base pads.

Abstract translation: 基座在支撑表面上以间距间隔开。 导电构件，可选择铜或其他金属柱，从基垫向上延伸到顶部焊盘。 顶部焊盘互连器以构造在基板之间的电感器电流路径的配置连接顶部焊盘。

公开(公告)号：US20190081607A1

公开(公告)日：2019-03-14

申请号：US15705035

申请日：2017-09-14

Applicant: QUALCOMM Incorporated

Inventor： Mario Francisco VELEZ ,  Niranjan Sunil MUDAKATTE ,  Jonghae KIM ,  Changhan Hobie YUN ,  David Francis BERDY ,  Shiqun GU ,  Chengjie ZUO

IPC: H03H7/01 ,  H01L49/02 ,  H01L23/532 ,  H03H3/00 ,  H01L27/01 ,  H01L23/522 ,  H01L23/528

Abstract: An integrated device that includes a substrate, a first interconnect over the substrate and a second interconnect comprising a first portion and a second portion. The integrated device further comprising a first dielectric layer between the first interconnect and the first portion of the second interconnect such that the first interconnect vertically overlaps with the first dielectric layer and the first portion of the second interconnect. The integrated device also includes a second dielectric layer formed over the substrate. The first interconnect, the first dielectric layer and the first portion of the second interconnect are configured to operate as a capacitor. The first portion and the second portion of the second interconnect are configured to operate as an inductor.

公开(公告)号：US20180167054A1

公开(公告)日：2018-06-14

申请号：US15379392

申请日：2016-12-14

Applicant: QUALCOMM Incorporated

Inventor： David Francis BERDY ,  Changhan Hobie YUN ,  Shiqun GU ,  Niranjan Sunil MUDAKATTE ,  Mario Francisco VELEZ ,  Chengjie ZUO ,  Jonghae KIM

IPC: H03H9/64 ,  H03H3/08 ,  H03H9/72

CPC classification number: H03H9/64 ,  H03H3/08 ,  H03H9/0523 ,  H03H9/0547 ,  H03H9/0561 ,  H03H9/059 ,  H03H9/72

Abstract: An integrated radio frequency (RF) circuit combines complementary features of passive devices and acoustic filters and includes a first die, a second die, and a third die. The first die includes a substrate having one or more passive devices. The second die includes a first acoustic filter. The second die is stacked and coupled to a first surface of the first die. The third die includes a second acoustic filter. The third die is stacked and coupled to a second surface opposite the first surface of the first die.

公开(公告)号：US20180090475A1

公开(公告)日：2018-03-29

申请号：US15275068

申请日：2016-09-23

Applicant: QUALCOMM Incorporated

Inventor： Chengjie ZUO ,  Jonghae KIM ,  David Francis BERDY ,  Changhan Hobie YUN ,  Niranjan Sunil MUDAKATTE ,  Mario Francisco VELEZ ,  Shiqun GU

IPC: H01L27/01 ,  H01L23/31 ,  H01L23/552 ,  H01L23/528 ,  H01L23/498 ,  H01L21/768 ,  H01L21/56 ,  H01L23/522 ,  H03H7/01 ,  H03H7/46 ,  H04B1/00

CPC classification number: H01L27/01 ,  H01L21/56 ,  H01L21/76885 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49805 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/552 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/14 ,  H01L2924/15313 ,  H01L2924/1815 ,  H01L2924/19011 ,  H01L2924/3025 ,  H03H7/0115 ,  H03H7/468 ,  H04B1/0057 ,  H01L2924/014 ,  H01L2924/00014

Abstract: An integrated circuit (IC) device includes a die having an integrated passive device (IPD) layer. The integrated circuit device also includes a substrate supporting the die, a molding compound surrounding the die. The integrated circuit device further includes a backside conductive layer on a surface of the die that is distal from the IPD layer. The integrated circuit device also includes vias coupling the backside conductive layer to a ground plane through the molding compound.

公开(公告)号：US20180077803A1

公开(公告)日：2018-03-15

申请号：US15261838

申请日：2016-09-09

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  David Francis BERDY ,  Chengjie ZUO ,  Jonghae KIM ,  Niranjan Sunil MUDAKATTE ,  Mario Francisco VELEZ ,  Shiqun GU

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/02 ,  H05K3/00 ,  H05K3/30 ,  H05K3/40

CPC classification number: H05K1/185 ,  H01G4/224 ,  H01G4/236 ,  H01G4/33 ,  H01L23/49822 ,  H01L23/52 ,  H05K1/162 ,  H05K3/4602 ,  H05K3/4682 ,  H05K3/4688

Abstract: Due to the presence of a glass substrate, it is difficult to fabricate thin conventional passive-on-glass (POG) devices. Also glass dicing has been a throughput bottleneck in fabricating the conventional POG device. To address such disadvantages, devices without the glass substrates are proposed. Support structures may be provided to provide mechanical support. The devices are significantly thinner and allow access to the passive components from both first and second surfaces, which are opposite and exposed surfaces. The proposed POM devices may also be incorporated in a package substrate.

公开(公告)号：US20170372989A1

公开(公告)日：2017-12-28

申请号：US15190164

申请日：2016-06-22

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  Mario Francisco VELEZ ,  Changhan Hobie YUN ,  David Francis BERDY ,  Chengjie ZUO ,  Jonghae KIM

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/60 ,  H01L23/31

CPC classification number: H01L23/49805 ,  H01L21/4846 ,  H01L23/3121 ,  H01L23/49811 ,  H01L2021/60007 ,  H01L2224/081 ,  H01L2224/09155 ,  H01L2224/16113 ,  H01L2224/16225

Abstract: A device package with a reduced foot print may include a substrate and a through-substrate via extending from a top surface to a bottom surface of the substrate. The assembly may also include a trace and a contact pad on the top and bottom surfaces of the substrate and electrically coupled to the through-substrate via. An encapsulated die above the substrate may be electrically coupled to the trace. A joint below the substrate may be electrically coupled to the contact pad. A sidewall of the through-substrate via may be exposed. At least a portion of the through-substrate via may be within an outer side boundary of the substrate. Also, the trace and the contact pad may be within the outer side boundary of the substrate.

公开(公告)号：US20170288707A1

公开(公告)日：2017-10-05

申请号：US15088019

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  David Francis BERDY ,  Chengjie ZUO ,  Daeik Daniel KIM ,  Mario Francisco VELEZ ,  Niranjan Sunil MUDAKATTE ,  Robert Paul MIKULKA

IPC: H04B1/00 ,  H03H3/00 ,  H03H7/01

CPC classification number: H04B1/0057 ,  H01L2224/11 ,  H03H3/00 ,  H03H7/0115 ,  H03H7/463 ,  H03H2001/0085

Abstract: A three dimensional (3D) multiplexer structure may include a first two dimensional (2D) inductor capacitor (LC) filter layer. The first 2D LC filter layer may include a first 2D spiral inductor and a first capacitor(s). The 3D multiplexer structure may also include a second 2D LC filter layer. The second 2D LC filter layer may include a second 2D spiral inductor and a second capacitor(s) stacked directly on and communicably coupled to the first 2D LC filter.

公开(公告)号：US20170187345A1

公开(公告)日：2017-06-29

申请号：US15067106

申请日：2016-03-10

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Daeik Daniel KIM ,  Mario Francisco VELEZ ,  Chengjie ZUO ,  David Francis BERDY ,  Jonghae KIM

IPC: H03H7/01 ,  H03H3/00 ,  H01P5/16 ,  H01Q1/50 ,  H01Q1/22

CPC classification number: H01P5/16 ,  H01Q1/22 ,  H01Q1/50 ,  H03H7/0115 ,  H03H7/463

Abstract: A multiplexer structure includes a passive substrate. The multiplexer structure may also include a high band filter on the passive substrate. The high band filter may include a 2D planar spiral inductor(s) on the passive substrate. The multiplexer structure may further include a low band filter on the passive substrate. The low band filter may include a 3D through-substrate inductor and a first capacitor(s) on the passive substrate. The multiplexer structure may also include a through substrate via(s) coupling the high band filter and the low band filter.