公开(公告)号：US08188787B2

公开(公告)日：2012-05-29

申请号：US11883039

申请日：2006-01-25

Applicant: Robin Wilson ,  David Miles

Inventor： Robin Wilson ,  David Miles

IPC: H03D1/00

CPC classification number: H03D1/18

Abstract: A demodulator for demodulating a modulated signal has a peak detector (206) with an input (100) coupled to receive the modulated signal and an output (207) to supply a peak detector output signal. The peak detector has a charge storer (314) coupled to the peak detector output so that the peak detector output signal is provided by a voltage across the charge storer (314) and a comparator (313) having a first comparator input coupled to the peak detector input to receive the modulated signal and a second comparator input coupled to the peak detector output to receive the peak detector output signal. The comparator (313) provides a comparison signal representing a comparison between the voltage of the modulated signal and the peak detector output signal. A charging controller (315, 316 and 318) charges the charge storer (314) so as to increase the output voltage when the comparator (313) provides a first signal indicating that the voltage of the modulated signal is higher than the voltage of the peak detector output signal and discharges the charge storer (314) so as to decrease the output voltage when the comparator (313) provides a second signal indicating that the voltage of the modulated signal is lower than the voltage of the peak detector output signal.

Abstract translation: 用于解调调制信号的解调器具有峰值检测器（206），其具有耦合以接收调制信号的输入（100）和输出（207）以提供峰值检测器输出信号。 峰值检测器具有耦合到峰值检测器输出的电荷存储器（314），使得峰值检测器输出信号由电荷存储器（314）两端的电压和比较器（313）提供，该比较器具有耦合到峰值的第一比较器输入端 检测器输入以接收调制信号，以及耦合到峰值检测器输出的第二比较器输入以接收峰值检测器输出信号。 比较器（313）提供表示调制信号的电压与峰值检测器输出信号之间的比较的比较信号。 当比较器（313）提供指示调制信号的电压高于峰值电压的第一信号时，充电控制器（315,316和318）对电荷存储器（314）充电，以增加输出电压 检测器输出信号，并且当比较器（313）提供指示调制信号的电压低于峰值检测器输出信号的电压的第二信号时，使电荷存储器（314）放电以便降低输出电压。

公开(公告)号：US20110266659A1

公开(公告)日：2011-11-03

申请号：US13179170

申请日：2011-07-08

Applicant: Robin Wilson ,  Conor Brogan ,  Hugh J. Griffin ,  Cormac MacNamara

Inventor： Robin Wilson ,  Conor Brogan ,  Hugh J. Griffin ,  Cormac MacNamara

IPC: H01L21/306 ,  H01L21/3065 ,  H01L29/06

CPC classification number: H01L21/78

Abstract: A semiconductor on insulator (SOI) wafer includes a semiconductor substrate having first and second main surfaces opposite to each other. A dielectric layer is disposed on at least a portion of the first main surface of the semiconductor substrate. A device layer has a first main surface and a second main surface. The second main surface of the device layer is disposed on a surface of the dielectric layer opposite to the semiconductor substrate. A plurality of intended die areas are defined on the first main surface of the device layer. The plurality of intended die areas are separated from one another. A plurality of die access trenches are formed in the semiconductor substrate from the second main surface. Each of the plurality of die access trenches are disposed generally beneath at least a respective one of the plurality of intended die areas.

Abstract translation: 绝缘体上半导体（SOI）晶片包括具有彼此相对的第一和第二主表面的半导体衬底。 电介质层设置在半导体衬底的第一主表面的至少一部分上。 器件层具有第一主表面和第二主表面。 器件层的第二主表面设置在与半导体衬底相对的电介质层的表面上。 在设备层的第一主表面上限定多个预期的管芯区域。 多个预期的模具区域彼此分离。 多个裸片存取沟槽从第二主表面形成在半导体衬底中。 多个管芯存取沟槽中的每一个通常设置在多个预期管芯区域中的至少一个相应的一个的下方。

公开(公告)号：US08030133B2

公开(公告)日：2011-10-04

申请号：US12413972

申请日：2009-03-30

Applicant: Robin Wilson

Inventor： Robin Wilson

IPC: H01L21/00 ,  H01L29/06

CPC classification number: H01L29/34 ,  B81C1/00952 ,  B81C2201/115 ,  H01L21/76251

Abstract: A method of manufacturing a semiconductor device includes providing first and second semiconductor substrates, each having first and second main surfaces opposite to one another. A roughened surface is formed on at least one of the first main surface of the first semiconductor substrate and the second main surface of the second semiconductor substrate. A dielectric layer is formed on the first main surface of the semiconductor substrate and the second semiconductor substrate is disposed on the dielectric layer opposite to the first semiconductor substrate. The second main surface of the second semiconductor substrate contacts the dielectric layer.

Abstract translation: 一种制造半导体器件的方法包括提供第一和第二半导体衬底，每个具有彼此相对的第一和第二主表面。 粗糙表面形成在第一半导体衬底的第一主表面和第二半导体衬底的第二主表面中的至少一个上。 电介质层形成在半导体衬底的第一主表面上，第二半导体衬底设置在与第一半导体衬底相对的电介质层上。 第二半导体衬底的第二主表面接触电介质层。

公开(公告)号：US20110199149A1

公开(公告)日：2011-08-18

申请号：US12986428

申请日：2011-01-07

Applicant: Robin Wilson ,  Sylvain Engels ,  Eric Balossier

Inventor： Robin Wilson ,  Sylvain Engels ,  Eric Balossier

IPC: H03K3/011

CPC classification number: G06F1/08 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic device may include a controlled generator configured to generate an adjustable frequency clock signal at at least one part of an integrated circuit coupled to the output of the controller generator and including at least one transistor having a gate of less than forty-five nanometers in length. The electronic device may include determination circuitry configured to determine the temperature of the at least one part of the integrated circuit, and drive circuitry coupled to the determination circuitry and configured to control the generator to increase the frequency of the clock signal when the temperature increases.

Abstract translation: 电子设备可以包括受控发电机，其被配置为在耦合到控制器发生器的输出的集成电路的至少一部分上产生可调节频率时钟信号，并且包括至少一个具有小于四十五纳米的栅极的晶体管 长度。 电子设备可以包括确定电路，其被配置为确定集成电路的至少一部分的温度，以及耦合到确定电路并被配置为当温度升高时控制发电机来增加时钟信号的频率的驱动电路。

公开(公告)号：US07999348B2

公开(公告)日：2011-08-16

申请号：US12203995

申请日：2008-09-04

Applicant: Robin Wilson ,  Conor Brogan ,  Hugh J. Griffin ,  Cormac MacNamara

Inventor： Robin Wilson ,  Conor Brogan ,  Hugh J. Griffin ,  Cormac MacNamara

IPC: H01L21/70

CPC classification number: H01L21/78

Abstract: A semiconductor on insulator (SOI) wafer includes a semiconductor substrate having first and second main surfaces opposite to each other. A dielectric layer is disposed on at least a portion of the first main surface of the semiconductor substrate. A device layer has a first main surface and a second main surface. The second main surface of the device layer is disposed on a surface of the dielectric layer opposite to the semiconductor substrate. A plurality of intended die areas are defined on the first main surface of the device layer. The plurality of intended die areas are separated from one another. A plurality of die access trenches are formed in the semiconductor substrate from the second main surface. Each of the plurality of die access trenches are disposed generally beneath at least a respective one of the plurality of intended die areas.

Abstract translation: 绝缘体上半导体（SOI）晶片包括具有彼此相对的第一和第二主表面的半导体衬底。 电介质层设置在半导体衬底的第一主表面的至少一部分上。 器件层具有第一主表面和第二主表面。 器件层的第二主表面设置在与半导体衬底相对的电介质层的表面上。 在设备层的第一主表面上限定多个预期的管芯区域。 多个预期的模具区域彼此分离。 多个裸片存取沟槽从第二主表面形成在半导体衬底中。 多个管芯存取沟槽中的每一个通常设置在多个预期管芯区域中的至少一个相应的一个的下方。

公开(公告)号：US07768085B2

公开(公告)日：2010-08-03

申请号：US11548546

申请日：2006-10-11

Applicant: Robin Wilson ,  Conor Brogan ,  Hugh J. Griffin ,  Cormac MacNamara

Inventor： Robin Wilson ,  Conor Brogan ,  Hugh J. Griffin ,  Cormac MacNamara

IPC: H01L31/113

CPC classification number: H01L27/14683 ,  H01L27/1463

Abstract: A photodetector array includes a semiconductor substrate having opposing first and second main surfaces, a first layer of a first doping concentration proximate the first main surface, and a second layer of a second doping concentration proximate the second main surface. The photodetector includes at least one conductive via formed in the first main surface and an anode/cathode region proximate the first main surface and the at least one conductive via. The via extends to the second main surface. The conductive via is isolated from the semiconductor substrate by a first dielectric material. The anode/cathode region is a second conductivity opposite to the first conductivity. The photodetector includes a doped isolation region of a third doping concentration formed in the first main surface and extending through the first layer of the semiconductor substrate to at least the second layer of the semiconductor substrate.

Abstract translation: 光电检测器阵列包括具有相对的第一和第二主表面的半导体衬底，靠近第一主表面的第一掺杂浓度的第一层和靠近第二主表面的第二掺杂浓度的第二层。 光电检测器包括形成在第一主表面中的至少一个导电通孔和靠近第一主表面和至少一个导电通孔的阳极/阴极区域。 通孔延伸到第二主表面。 导电通孔通过第一电介质材料与半导体衬底隔离。 阳极/阴极区域是与第一导电性相反的第二导电性。 光电检测器包括形成在第一主表面中并延伸穿过半导体衬底的第一层的至少第二层半导体衬底的第三掺杂浓度的掺杂隔离区。

公开(公告)号：US07601556B2

公开(公告)日：2009-10-13

申请号：US12116638

申请日：2008-05-07

Applicant: Robin Wilson ,  Conor Brogan ,  Hugh J. Griffin ,  Cormac MacNamara

Inventor： Robin Wilson ,  Conor Brogan ,  Hugh J. Griffin ,  Cormac MacNamara

IPC: H01L21/00

CPC classification number: H01L27/1446 ,  H01L31/022408

Abstract: A photodiode includes a semiconductor having front and backside surfaces and first and second active layers of opposite conductivity, separated by an intrinsic layer. A plurality of isolation trenches filled with conductive material extend into the first active layer, dividing the photodiode into a plurality of cells and forming a central trench region in electrical communication with the first active layer beneath each of the cells. Sidewall active diffusion regions extend the trench depth along each sidewall and are formed by doping at least a portion of the sidewalls with a dopant of first conductivity. A first contact electrically communicates with the first active layer beneath each of the cells via the central trench region. A plurality of second contacts each electrically communicate with the second active layer of one of the plurality of cells. The first and second contacts are formed on the front surface of the photodiode.

Abstract translation: 光电二极管包括具有前后表面的半导体以及由本征层隔开的相反电导率的第一和第二有源层。 填充有导电材料的多个隔离沟槽延伸到第一有源层中，将光电二极管分成多个单元并形成与每个单元下面的第一有源层电连通的中心沟槽区。 侧壁有源扩散区域沿着每个侧壁延伸沟槽深度，并且通过用第一导电性的掺杂剂掺杂至少一部分侧壁而形成。 第一接触件经由中心沟槽区域与每个电池单元之下的第一有源层电连通。 多个第二触点分别与多个单元之一的第二活性层电连通。 第一和第二触点形成在光电二极管的前表面上。

公开(公告)号：US07579667B2

公开(公告)日：2009-08-25

申请号：US12191035

申请日：2008-08-13

Applicant: Conor Brogan ,  Cormac MacNamara ,  Hugh J. Griffin ,  Robin Wilson

Inventor： Conor Brogan ,  Cormac MacNamara ,  Hugh J. Griffin ,  Robin Wilson

IPC: H01L31/00 ,  H01L21/44

CPC classification number: H01L21/2007 ,  H01L21/76251 ,  H01L29/0634 ,  H01L29/66143 ,  H01L29/872

Abstract: A bonded-wafer semiconductor device includes a semiconductor substrate, a buried oxide layer disposed on a first main surface of the semiconductor substrate and a multi-layer device stack. The multi-layer device stack includes a first device layer of a first conductivity disposed on the buried oxide layer, a second device layer of a second conductivity disposed on the first device layer, a third device layer of the first conductivity disposed on the second device layer and a fourth device layer of the second conductivity disposed on the third device layer. A trench is formed in the multi-layer device stack. A mesa is defined by the trench. The mesa has first and second sidewalls. A first anode/cathode layer is disposed on a first sidewall of the multi-layer device stack, and a second anode/cathode layer is disposed on the second sidewall of the multi-layer device stack.

Abstract translation: 接合晶片半导体器件包括半导体衬底，设置在半导体衬底的第一主表面上的掩埋氧化物层和多层器件堆叠。 多层器件堆叠包括设置在掩埋氧化物层上的第一导电体的第一器件层，设置在第一器件层上的第二导电体的第二器件层，设置在第二器件上的第一导电体的第三器件层 层和设置在第三器件层上的第二导电体的第四器件层。 在多层器件堆叠中形成沟槽。 台面由沟槽定义。 台面具有第一和第二侧壁。 第一阳极/阴极层设置在多层器件堆叠的第一侧壁上，第二阳极/阴极层设置在多层器件堆叠的第二侧壁上。

公开(公告)号：US07579273B2

公开(公告)日：2009-08-25

申请号：US11837150

申请日：2007-08-10

Applicant: Robin Wilson ,  Conor Brogan ,  Hugh J. Griffin ,  Cormac MacNamara

Inventor： Robin Wilson ,  Conor Brogan ,  Hugh J. Griffin ,  Cormac MacNamara

IPC: H01L21/44

CPC classification number: H01L27/1446 ,  H01L21/76898 ,  H01L31/18

Abstract: A method for manufacturing a photodiode array includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has a first layer of a first conductivity proximate the first main surface and a second layer of a second conductivity proximate the second main surface. A via is formed in the substrate which extends to a first depth position relative to the first main surface. The via has a first aspect ratio. Generally simultaneously with forming the via, an isolation trench is formed in the substrate spaced apart from the via which extends to a second depth position relative to the first main surface. The isolation trench has a second aspect ratio different from the first aspect ratio.

Abstract translation: 一种制造光电二极管阵列的方法包括提供具有彼此相对的第一和第二主表面的半导体衬底。 半导体衬底具有靠近第一主表面的第一导电的第一层和靠近第二主表面的第二导电的第二层。 在衬底中形成通孔，该通孔相对于第一主表面延伸到第一深度位置。 通孔具有第一宽高比。 通常在形成通孔的同时，在与通孔间隔开的基板中形成隔离沟槽，其相对于第一主表面延伸到第二深度位置。 隔离沟槽具有与第一宽高比不同的第二宽高比。

公开(公告)号：US20090176330A1

公开(公告)日：2009-07-09

申请号：US12371015

申请日：2009-02-13

Applicant: Robin Wilson ,  Conor Brogan ,  Hugh J. Griffin ,  Cormac MacNamara

Inventor： Robin Wilson ,  Conor Brogan ,  Hugh J. Griffin ,  Cormac MacNamara

IPC: H01L31/02 ,  H01L31/18

CPC classification number: H01L27/1446 ,  H01L27/14603 ,  H01L27/1463 ,  H01L27/14683 ,  H01L31/105

Abstract: A photodiode having an increased proportion of light-sensitive area to light-insensitive area includes a semiconductor having a backside surface and a light-sensitive frontside surface. The semiconductor includes a first active layer having a first conductivity, a second active layer having a second conductivity opposite the first conductivity, and an intrinsic layer separating the first and second active layers. A plurality of isolation trenches are arranged to divide the photodiode into a plurality of cells. Each cell has a total frontside area including a cell active frontside area sensitive to light and a cell inactive frontside area not sensitive to light. The cell active frontside area forms at least 95 percent of the cell total frontside area. A method of forming the photodiode is also disclosed.

Abstract translation: 光敏面积比例增加到光不敏感区域的光电二极管包括具有背面和感光前侧表面的半导体。 半导体包括具有第一导电性的第一有源层，具有与第一导电性相反的第二导电性的第二有源层和分离第一和第二有源层的本征层。 布置多个隔离沟以将光电二极管分成多个单元。 每个细胞具有包括对光敏感的细胞活性前方区域和对光不敏感的细胞非活动的前侧区域的总前方区域。 细胞活动前方区域形成至少95％的细胞总前方区域。 还公开了一种形成光电二极管的方法。