公开(公告)号：US11062751B2

公开(公告)日：2021-07-13

申请号：US16704320

申请日：2019-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee Cho ,  Woobin Song ,  Hyunmog Park ,  Sangkil Lee

IPC: G11C11/22 ,  G11C11/00 ,  H01L27/1159 ,  H01L27/108 ,  G11C11/4096 ,  H01L27/11592

Abstract: A memory device includes a substrate including first and second regions, the first region having first wordlines and first bitlines, and the second region having second wordlines and second bitlines, a first memory cell array including first memory cells in the first region, the first memory cell array having volatility, and each of the first memory cells including a cell switch having a first channel region adjacent to a corresponding first wordline of the first wordlines, and a capacitor connected to the cell switch, and a second memory cell array including second memory cells in the second region, the second memory cell array having non-volatility, and each of the second memory cells including a second channel region adjacent to a corresponding second wordline of the second wordlines, and a ferroelectric layer between the corresponding second wordline of the second wordlines and the second channel region.

公开(公告)号：US20190296018A1

公开(公告)日：2019-09-26

申请号：US16185892

申请日：2018-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Cho ,  Junsoo Kim ,  Ho Lee ,  Chankyung Kim ,  Hei Seung Kim ,  Jaehong Min ,  Sangwuk Park ,  Woo Bin Song ,  Sang Woo Lee

IPC: H01L27/108

Abstract: A semiconductor device can include a semiconductor substrate and an active region in the semiconductor substrate, where the active region can include an oxide semiconductor material having a variable atomic concentration of oxygen. A first source/drain region can be in the active region, where the first source/drain region can have a first atomic concentration of oxygen in the oxide semiconductor material. A second source/drain region can be in the active region spaced apart from first source/drain region and a channel region can be in the active region between the first source/drain region and the second source/drain region, where the channel region can have a second atomic concentration of oxygen in the oxide semiconductor material that is less than the first atomic concentration of oxygen. A gate electrode can be on the channel region and extend between the first source/drain region and the second source/drain region.

公开(公告)号：US20240276703A1

公开(公告)日：2024-08-15

申请号：US18517126

申请日：2023-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonsok Lee ,  Juho Lee ,  Seunghyun Kim ,  Wooje Jung ,  Minhee Cho

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/033 ,  H10B12/05

Abstract: A semiconductor memory device, which may include a substrate, a lower conductive line on the substrate, an isolation insulating layer on the lower conductive line and including a channel trench, a channel structure inside the channel trench and including a first oxide semiconductor material, an interfacial conductive pattern between the lower conductive line and a lower surface of the channel structure, a gate dielectric layer that covers the channel structure within the channel trench, an upper conductive line on the gate dielectric layer within the channel trench, a conductive contact pattern on the channel structure, an interfacial oxide semiconductor pattern between the channel structure and the conductive contact pattern and including a second oxide semiconductor material, and a capacitor structure including a lower electrode connected to the conductive contact pattern.

公开(公告)号：US20240224494A1

公开(公告)日：2024-07-04

申请号：US18414893

申请日：2024-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Ilgweon Kim ,  Huijung Kim ,  Sungwon Yoo ,  Minhee Cho

IPC: H10B12/00

CPC classification number: H10B12/00

Abstract: A semiconductor memory device includes: a first word line extending in a vertical direction; a second word line spaced apart from the first word line in a first horizontal direction and extending in the vertical direction; a first semiconductor pattern of a ring-shaped horizontal cross-section surrounding the first word line and constituting a portion of a first cell transistor; a second semiconductor pattern of a ring-shaped horizontal cross-section surrounding the second word line and constituting a portion of a second cell transistor; a cell capacitor between the first semiconductor pattern and the second semiconductor pattern and including a first electrode, a second electrode, and a capacitor dielectric film; a first bit line opposite the cell capacitor with respect to the first semiconductor pattern and extending in a second horizontal direction; and a second bit line opposite the cell capacitor with respect to the second semiconductor pattern.

公开(公告)号：US11917805B2

公开(公告)日：2024-02-27

申请号：US17541584

申请日：2021-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan Lee ,  Yongseok Kim ,  Ilgweon Kim ,  Huijung Kim ,  Sungwon Yoo ,  Minhee Cho

IPC: H10B12/00

CPC classification number: H10B12/00

Abstract: A semiconductor memory device includes: a first word line extending in a vertical direction; a second word line spaced apart from the first word line in a first horizontal direction and extending in the vertical direction; a first semiconductor pattern of a ring-shaped horizontal cross-section surrounding the first word line and constituting a portion of a first cell transistor; a second semiconductor pattern of a ring-shaped horizontal cross-section surrounding the second word line and constituting a portion of a second cell transistor; a cell capacitor between the first semiconductor pattern and the second semiconductor pattern and including a first electrode, a second electrode, and a capacitor dielectric film; a first bit line opposite the cell capacitor with respect to the first semiconductor pattern and extending in a second horizontal direction; and a second bit line opposite the cell capacitor with respect to the second semiconductor pattern.

公开(公告)号：US11342456B2

公开(公告)日：2022-05-24

申请号：US17144444

申请日：2021-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woobin Song ,  Heiseung Kim ,  Mirco Cantoro ,  Sangwoo Lee ,  Minhee Cho ,  Beomyong Hwang

IPC: H01L29/78 ,  H01L29/161 ,  H01L21/02 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28

Abstract: A ferroelectric semiconductor device includes an active region extending in one direction, a gate insulating layer crossing the active region, a ferroelectric layer disposed on the gate insulating layer and including a hafnium oxide, a gate electrode layer disposed on the ferroelectric layer, and source/drain regions disposed on the active region to be adjacent to both sides of the gate insulating layer, wherein the ferroelectric layer includes 20% or more of orthorhombic crystals, and an upper surface of the source/drain region is located at a level equal to or higher than an upper surface of the ferroelectric layer.