公开(公告)号：US20190075662A1

公开(公告)日：2019-03-07

申请号：US16181180

申请日：2018-11-05

Applicant: SANMINA CORPORATION

Inventor： Shinichi Iketani ,  Dale Kersten

IPC: H05K3/42 ,  H05K1/11 ,  H05K1/02

CPC classification number: H05K3/429 ,  H05K1/0251 ,  H05K1/115 ,  H05K2201/0187 ,  H05K2201/09536 ,  H05K2201/09645 ,  H05K2203/061 ,  H05K2203/0713 ,  Y10T29/49165

Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

公开(公告)号：US20180092222A1

公开(公告)日：2018-03-29

申请号：US15723135

申请日：2017-10-02

Applicant: SANMINA CORPORATION

Inventor： Shinichi Iketani ,  Dale Kersten

IPC: H05K3/42 ,  H05K1/11

CPC classification number: H05K3/429 ,  H05K1/0251 ,  H05K1/115 ,  H05K2201/0187 ,  H05K2201/09536 ,  H05K2201/09645 ,  H05K2203/061 ,  H05K2203/0713 ,  Y10T29/49165

Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

公开(公告)号：US09781844B2

公开(公告)日：2017-10-03

申请号：US14205331

申请日：2014-03-11

Applicant: SANMINA CORPORATION

Inventor： Shinichi Iketani ,  Dale Kersten

IPC: H05K3/42 ,  H05K1/11 ,  H05K1/02

CPC classification number: H05K3/429 ,  H05K1/0251 ,  H05K1/115 ,  H05K2201/0187 ,  H05K2201/09536 ,  H05K2201/09645 ,  H05K2203/061 ,  H05K2203/0713 ,  Y10T29/49165

Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

公开(公告)号：US20150047188A1

公开(公告)日：2015-02-19

申请号：US14463588

申请日：2014-08-19

Applicant: Sanmina Corporation

Inventor： Douglas Ward Thomas ,  Shinichi Iketani

IPC: H05K3/42

CPC classification number: H05K3/427 ,  H05K3/0026 ,  H05K3/0047 ,  H05K2201/09845 ,  H05K2203/0207 ,  Y10T29/49165

Abstract: Cost effective and efficient methods to maximize printed circuit board (PCB) utilization with minimized signal degradation are provided. The methods include electrically isolating a segmented via structure by controlling the formation of a conductive material within a plated via structure by utilizing different diameter drills within a via structure for trimming the conductive material at the via shoulder (i.e., the rim of a drilled two diameter hole boundary). The trimmed portion may be voided in the via structure for allowing electrically isolated plated through-hole (PTH) segments. One or more areas of trimmed rims within the via structure are used to form multiple stair like diameter holes to create one or more voids in the via structure. As a result, the formation of conductive material within the via structure may be limited to those areas necessary for the transmission of electrical signals.

Abstract translation: 提供了以最小的信号劣化来最大化印刷电路板（PCB）利用率的成本有效和高效的方法。 所述方法包括通过在通孔结构内利用不同直径的钻头来控制在通孔结构内的导电材料的形成来控制电镀过孔结构内的导电材料的形成来电隔离分段通孔结构，以用于修整通孔肩部处的导电材料（即，钻孔两个直径的边缘 孔边界）。 修整部分可以在通孔结构中被排除，以允许电隔离的电镀通孔（PTH）段。 通孔结构内的一个或多个修剪边缘的区域用于形成多个阶梯状直径孔，以在通孔结构中产生一个或多个空隙。 结果，通孔结构内的导电材料的形成可以限于传输电信号所需的那些区域。

公开(公告)号：US11304311B2

公开(公告)日：2022-04-12

申请号：US17080524

申请日：2020-10-26

Applicant: SANMINA CORPORATION

Inventor： Shinichi Iketani ,  Drew Doblar

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/42

Abstract: A multilayer printed circuit board is provided having a first conductive layer and a first plating resist selectively positioned within the first conductive layer. A second plating resist may be selectively positioned within a second conductive layer. A through hole extends through the first plating resist in the first conductive layer and the second plating resist in the second conductive layer. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

公开(公告)号：US11246226B2

公开(公告)日：2022-02-08

申请号：US16298896

申请日：2019-03-11

Applicant: Sanmina Corporation

Inventor： Shinichi Iketani ,  Dale Kersten

IPC: H01K3/10 ,  H05K3/42 ,  H05K1/11 ,  H05K3/00

Abstract: Laminate structures including hole plugs, and methods for forming a hole plug in a laminate structure are provided. A laminate structure may be formed with at least a dielectric layer and a first conductive foil on a first side of the dielectric layer. A blind hole may be formed in the laminate structure extending toward the first conductive foil from a second side of the dielectric layer and at least partially through the dielectric layer, the blind hole including a hole depth to hole diameter aspect ratio of less than ten (10) to one (1). Via fill ink may be disposed in the blind hole, and the via fill ink may be dried and/or cured to form a hole plug.

公开(公告)号：US20210153360A1

公开(公告)日：2021-05-20

申请号：US17080524

申请日：2020-10-26

Applicant: SANMINA CORPORATION

Inventor： Shinichi Iketani ,  Drew Doblar

IPC: H05K3/42 ,  H05K1/11

Abstract: A multilayer printed circuit board is provided having a first conductive layer and a first plating resist selectively positioned within the first conductive layer. A second plating resist may be selectively positioned within a second conductive layer. A through hole extends through the first plating resist in the first conductive layer and the second plating resist in the second conductive layer. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

公开(公告)号：US10820427B2

公开(公告)日：2020-10-27

申请号：US16518967

申请日：2019-07-22

Applicant: SANMINA CORPORATION

Inventor： Shinichi Iketani ,  Drew Doblar

IPC: H05K3/42 ,  H05K1/11 ,  H05K1/02

Abstract: A multilayer printed circuit board is provided having a first conductive layer and a first plating resist selectively positioned within the first conductive layer. A second plating resist may be selectively positioned within a second conductive layer. A through hole extends through the first plating resist in the first conductive layer and the second plating resist in the second conductive layer. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

公开(公告)号：US20200043690A1

公开(公告)日：2020-02-06

申请号：US16601068

申请日：2019-10-14

Applicant: SANMINA CORPORATION

Inventor： Shinichi Iketani ,  Douglas Ward Thomas

IPC: H01H85/12 ,  H05K3/46 ,  H05K3/40 ,  H05K3/10 ,  H05K3/00 ,  H05K1/14 ,  H05K1/11 ,  H01H85/56 ,  H01H85/30 ,  H01H85/20 ,  H01H85/055 ,  H01H85/143 ,  H01H85/00

Abstract: A method of making printed circuit board vias using a double drilling and plating method is disclosed. A first hole is drilled in a core, the first hole having a first diameter. The first hole is filled and/or plated with an electrically conductive material. A circuit pattern may be formed on one or two conductive layers of the core. A multilayer structure may then be formed including a plurality of cores that also include pre-drilled and plated via holes, wherein at least some of the pre-drilled and plated via holes are aligned with the first hole. A second hole is then drilled within the first hole and the aligned pre-drilled and plated holes, the second hole having a second diameter where the second diameter is smaller than the first diameter. A conductive material is then plated to an inner surface of the second hole.

公开(公告)号：US20200015364A1

公开(公告)日：2020-01-09

申请号：US16518967

申请日：2019-07-22

Applicant: SANMINA CORPORATION

Inventor： Shinichi Iketani ,  Drew Doblar

IPC: H05K3/42 ,  H05K1/11

Abstract: A multilayer printed circuit board is provided having a first conductive layer and a first plating resist selectively positioned within the first conductive layer. A second plating resist may be selectively positioned within a second conductive layer. A through hole extends through the first plating resist in the first conductive layer and the second plating resist in the second conductive layer. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.