公开(公告)号：US20240206159A1

公开(公告)日：2024-06-20

申请号：US18454105

申请日：2023-08-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjung Lee ,  Dongsik Kong ,  Junsoo Kim ,  Junbum Lee ,  Jinseong Lee

IPC: H10B12/00

CPC classification number: H10B12/488 ,  H10B12/053 ,  H10B12/34

Abstract: Integrated circuit devices may include a substrate including a word line trench extending longitudinally in a first horizontal direction, a gate dielectric film extending along an inner surface of the word line trench, a word line in a lower portion of the word line trench on the gate dielectric film and extending longitudinally in the first horizontal direction, and an insulating capping pattern in an upper portion of the word line trench on the word line and extending longitudinally in the first horizontal direction. The word line may include a work-function control conductive plug including a conductive metal nitride that include a metal dopant, and the work-function control conductive plug includes a top surface in contact with a bottom surface of the insulating capping pattern, a sidewall in contact with the gate dielectric film, and a bottom surface in contact with a monolithic layer.

公开(公告)号：US20240136396A1

公开(公告)日：2024-04-25

申请号：US18141990

申请日：2023-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiho Yoo ,  Kihyung Ko ,  Junsoo Kim ,  Hyunsup Kim ,  Jihoon Cha

IPC: H01L29/06 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/775

Abstract: A semiconductor device may include an active pattern on a substrate; an isolation pattern on the substrate, the isolation pattern covering opposite sidewalls of the active pattern; a liner on the isolation pattern, a liner including a material different from the isolation pattern; a gate structure contacting an upper surface of the active pattern and an upper surface of the liner; and a plurality of channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the plurality of channels extending through the gate structure.

公开(公告)号：US11830539B2

公开(公告)日：2023-11-28

申请号：US17935121

申请日：2022-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junsoo Kim ,  Minwoo Kwon

IPC: G11C11/24 ,  G11C11/408 ,  H10B12/00

CPC classification number: G11C11/4085 ,  H10B12/30 ,  H10B12/50

Abstract: An integrated circuit device includes a plurality of memory cells each including a channel region, a first sub-word line, a second sub-word line, and a storage element. A word line driving circuit is configured to drive the first and sub-word lines. The word line driving circuit includes a PMOS transistor, an NMOS transistor, a keeping NMOS transistor, and a first keeping PMOS transistor. A negative voltage is applied to a source of the NMOS transistor, the negative voltage is applied to a source of the keeping NMOS transistor, the first sub-word line is connected to a source of the first keeping PMOS transistor, the second sub-word line is connected to a drain of the first keeping PMOS transistor, and a negative voltage is applied to a gate of the first keeping PMOS transistor.

公开(公告)号：US11626409B2

公开(公告)日：2023-04-11

申请号：US17318563

申请日：2021-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Huijung Kim ,  Minwoo Kwon ,  Sangyeon Han ,  Sangwon Kim ,  Junsoo Kim ,  Hyeonjin Shin ,  Eunkyu Lee

IPC: H01L27/108 ,  H01L29/423 ,  H01L29/78

Abstract: A semiconductor device includes a substrate including an active region, a gate structure disposed in a gate trench in the substrate, a bit line disposed on the substrate and electrically connected to the active region on one side of the gate structure, and a capacitor disposed on the bit line and electrically connected to the active region on another side of the gate structure. The gate structure includes a gate dielectric layer disposed on bottom and inner side surfaces of the gate trench, a conductive layer disposed on the gate dielectric layer in a lower portion of the gate trench, sidewall insulating layers disposed on the gate dielectric layer, on an upper surface of the conductive layer, a graphene conductive layer disposed on the conductive layer, and a buried insulating layer disposed between the sidewall insulating layers on the graphene conductive layer.

公开(公告)号：US11508733B2

公开(公告)日：2022-11-22

申请号：US16744871

申请日：2020-01-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungjun Noh ,  Junsoo Kim ,  Dongsoo Woo ,  Namho Jeon

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L27/108 ,  H01L29/66 ,  H01L21/285 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/528 ,  H01L29/51 ,  H01L21/3115 ,  H01L21/265 ,  H01L21/28 ,  H01L21/02 ,  H01L21/3065

Abstract: An integrated circuit device includes: a substrate including active regions; a device isolation film defining the active regions; a word line arranged over the active regions and the device isolation film and extending in a first horizontal direction; and a gate dielectric film arranged between the substrate and the word line and between the device isolation film and the word line, in which, in a second horizontal direction orthogonal to the first horizontal direction, a width of a second portion of the word line over the device isolation film is greater than a width of a first portion of the word line over the active regions. To manufacture the integrated circuit device, an impurity region is formed in the substrate and the device isolation film by implanting dopant ions into the substrate and the device isolation film, and a thickness of a portion of the impurity region is reduced.

公开(公告)号：US10886375B2

公开(公告)日：2021-01-05

申请号：US16288910

申请日：2019-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin Lee ,  Junsoo Kim ,  Moonyoung Jeong ,  Satoru Yamada ,  Dongsoo Woo ,  Jiyoung Kim

IPC: H01L29/40 ,  H01L29/423 ,  H01L27/108 ,  H01L21/84 ,  H01L29/775 ,  H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  B82Y10/00 ,  H01L27/088

Abstract: A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.

公开(公告)号：US10431680B2

公开(公告)日：2019-10-01

申请号：US15391888

申请日：2016-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungsam Lee ,  Junsoo Kim ,  Hyoshin Ahn ,  Satoru Yamada ,  Joohyun Jeon ,  MoonYoung Jeong ,  Chunhyung Chung ,  Min Hee Cho ,  Kyo-Suk Chae ,  Eunae Choi

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/04

Abstract: A semiconductor device including a semiconductor substrate including a trench, the semiconductor substrate having a crystal structure; and an insulating layer covering an inner sidewall of the trench, wherein the inner sidewall of the trench has at least one plane included in a {320} family of planes of the crystal structure or at least one plane similar to the {320} family of planes.

公开(公告)号：US20250040124A1

公开(公告)日：2025-01-30

申请号：US18442274

申请日：2024-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongsik Kong ,  Sungho Jang ,  Junsoo Kim ,  Junbum Lee ,  Jaehyun Choi ,  Ilgweon Kim ,  Jeonghoon Oh

IPC: H10B12/00

Abstract: A gate structure includes a gate electrode on a substrate, the gate electrode including a lower portion and an upper portion sequentially stacked in a first direction substantially perpendicular to an upper surface of the substrate; a spacer structure including a second spacer and a first spacer sequentially stacked in a second direction substantially parallel to the upper surface of the substrate on a sidewall of the upper portion of the gate electrode; and a gate insulation pattern on a lower surface and a sidewall of the lower portion of the gate electrode and an outer sidewall of the spacer structure; wherein a cross-section of the first spacer has a shape of an “L”, and wherein the second spacer includes a material that is configured to induce a dipole at an interface of the first spacer and the gate insulation pattern.

公开(公告)号：US20230422479A1

公开(公告)日：2023-12-28

申请号：US18133964

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeesun Lee ,  Junsoo Kim ,  Daehyun Moon ,  Namhyun Lee ,  Seonhaeng Lee ,  Sungho Jang ,  Joohyun Jeon ,  Joon Han

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/34 ,  H10B12/482

Abstract: A semiconductor device includes a first active pattern included in an upper portion of a substrate in a memory cell region, and having an isolated shape extending so that a direction oblique to a first direction is a major axis direction of the first active pattern. A first device isolation pattern provided inside a first trench included in the substrate, and covering a side wall of the first active pattern is provided. A first gate structure is provided inside a gate trench extending in the first direction on upper portions of the first active pattern and the first device isolation pattern. A barrier impurity region is selectively formed only on surfaces of both side walls of a major axis of the first active pattern. First and second impurity regions are provided on the upper portion of the first active pattern adjacent to both sides of the first gate structure.

公开(公告)号：US11844212B2

公开(公告)日：2023-12-12

申请号：US17748261

申请日：2022-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Junsoo Kim ,  Hui-Jung Kim ,  Bong-Soo Kim ,  Satoru Yamada ,  Kyupil Lee ,  Sunghee Han ,  HyeongSun Hong ,  Yoosang Hwang

IPC: H10B41/27 ,  H01L23/532 ,  G11C7/18 ,  G11C8/14 ,  H10B41/35 ,  G11C11/404 ,  G11C11/4097 ,  H01L49/02

CPC classification number: H10B41/27 ,  G11C7/18 ,  G11C8/14 ,  H01L23/53295 ,  H01L28/60 ,  H10B41/35 ,  G11C11/404 ,  G11C11/4097

Abstract: A semiconductor memory device includes a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also includes a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer includes semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.