公开(公告)号：US11797396B2

公开(公告)日：2023-10-24

申请号：US16944039

申请日：2020-07-30

Applicant: Seagate Technology LLC

Inventor： Deepak Sridhara ,  Jason Bellorado ,  Ara Patapoutian ,  Marcus Marrow

IPC: G06F11/14 ,  G06F11/07 ,  G06F3/06

CPC classification number: G06F11/1471 ,  G06F3/064 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/0772

Abstract: An error recovery process provides for selecting a first recovery scheme for a decoding attempt on a first subset of a set of failed data blocks read from a data track; selecting a second different recovery scheme for a decoding attempt on a second subset of the set of failed data blocks read from the data track; and during a single revolution of the data track, performing operations to decode a first subset of the failed data blocks according to the first recovery scheme operations to decode the second subset of the failed data blocks according to the second different recovery scheme.

公开(公告)号：US11658669B2

公开(公告)日：2023-05-23

申请号：US17582376

申请日：2022-01-24

Applicant: Seagate Technology LLC

Inventor： Jason Bellorado ,  Marcus Marrow ,  Zheng Wu

IPC: G11B20/10 ,  G11B5/00 ,  H03M1/06 ,  H03G3/30 ,  G11B5/027 ,  G11B5/012

CPC classification number: H03M1/06 ,  G11B5/012 ,  G11B5/027 ,  G11B20/10324 ,  H03G3/30 ,  H03G2201/103

Abstract: Systems and methods are disclosed for magnetoresistive asymmetry (MRA) compensation using a digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing analog offset compensation to constrain an extremum of the analog signal to adjust a dynamic range based on an input range of an analog-to-digital converter (ADC), rather than to modify the analog signal to have a zero mean. The method may further comprise converting the analog signal to a digital sample sequence via the ADC; performing, via a digital MRA compensation circuit, digital MRA compensation on the digital sample sequence; receiving, via a digital backend (DBE) subsystem, the digital sample sequence prior to digital MRA compensation; and generating, via a DBE, a bit sequence corresponding to the analog signal based on an output of the DBE subsystem and an output of the digital MRA compensation circuit.

公开(公告)号：US11646057B2

公开(公告)日：2023-05-09

申请号：US17409927

申请日：2021-08-24

Applicant: Seagate Technology LLC

Inventor： Zheng Wang ,  Ara Patapoutian ,  Timothy F. Ellis ,  Jason Bellorado ,  William M. Radich

IPC: G11B5/60 ,  G11B20/12 ,  G11B20/10 ,  G11B5/596 ,  G11B5/55

CPC classification number: G11B5/6029 ,  G11B5/5565 ,  G11B5/59622 ,  G11B5/607 ,  G11B20/10518 ,  G11B20/1258

Abstract: Two or more data values are received from one or more sensors of a hard disk drive. The two or more data values are indicative of a fly height of a recording head of the hard disk drive. The two or more data values are input into a machine-learning processor during operation of the hard disk drive. A fly height of the recording head during the operation of the hard drive head is adjusted based on an output of the machine learning processor.

公开(公告)号：US20230062615A1

公开(公告)日：2023-03-02

申请号：US17409927

申请日：2021-08-24

Applicant: Seagate Technology LLC

Inventor： Zheng Wang ,  Ara Patapoutian ,  Timothy F. Ellis ,  Jason Bellorado ,  William M. Radich

IPC: G11B5/60 ,  G06N3/08 ,  G11B5/55 ,  G11B20/10 ,  G11B5/596 ,  G11B20/12

Abstract: Two or more data values are received from one or more sensors of a hard disk drive. The two or more data values are indicative of a fly height of a recording head of the hard disk drive. The two or more data values are input into a machine-learning processor during operation of the hard disk drive. A fly height of the recording head during the operation of the hard drive head is adjusted based on an output of the machine learning processor

公开(公告)号：US11568895B1

公开(公告)日：2023-01-31

申请号：US17466327

申请日：2021-09-03

Applicant: Seagate Technology LLC

Inventor： Ara Patapoutian ,  Zheng Wang ,  Jason Bellorado ,  William M. Radich

IPC: G11B21/10 ,  G11B20/10 ,  G11B5/012

Abstract: A method includes determining an error after attempting to read, via a first read transducer and a second read transducer, a data sector in a first data track. The method further includes calculating a weight ratio associated with the data sector and determining a read offset direction of the data sector based, at least in part, on the calculated weight ratio.

公开(公告)号：US11562767B1

公开(公告)日：2023-01-24

申请号：US17469301

申请日：2021-09-08

Applicant: Seagate Technology LLC

Inventor： Ara Patapoutian ,  Jason Bellorado ,  Zheng Wang ,  William M. Radich

IPC: G11B20/18 ,  G11B5/56 ,  G11B5/55 ,  G11B5/02 ,  G11B5/596

Abstract: An integrated circuit includes a read/write channel and a servo controller. The read/write channel is configured to: determine, in connection with a first path, respective read errors associated with N number of the data sectors; estimate respective offset positions of the N number of the data sectors; and generate a second path based, at least in part, on the respective estimated offset positions. The servo controller is configured to cause adjustment of a position of a read transducer based on the second path.

公开(公告)号：US20220399037A1

公开(公告)日：2022-12-15

申请号：US17890580

申请日：2022-08-18

Applicant: Seagate Technology LLC

Inventor： Jason Bellorado ,  Marcus Marrow ,  Zheng Wu

IPC: G11B5/596 ,  G11B5/012

Abstract: Systems and methods are disclosed for synchronous writing of a grain patterned medium. The systems and methods can be implemented within a data storage device having a grain patterned medium. Further, a calibration process to determine a count of bits between servo wedges can be implemented in manufacturing, within the data storage device, or both. In some examples, the data storage device, during operation, can utilize the count of bits to perform synchronous writing, determine write errors, or both. Further, the servo wedge of the grain patterned medium may be patterned with a same or similar grain pattern as the data area that follows the servo wedge. Such a data storage device can implement a single clock for reading a servo wedge and writing a data area.

公开(公告)号：US10936003B1

公开(公告)日：2021-03-02

申请号：US15803672

申请日：2017-11-03

Applicant: Seagate Technology LLC

Inventor： Zheng Wu ,  Jason Bellorado ,  Marcus Marrow ,  Trung Thuc Nguyen ,  Wing Fai Hui ,  Kin Ming Chan

IPC: G06F1/08 ,  G06F1/12 ,  H03L7/07 ,  H03L7/093 ,  H03L7/095

Abstract: Systems and methods are disclosed for phase locking multiple clocks of different frequencies. In certain embodiments, an apparatus may be configured to downsample a first clock having a first frequency and a second clock having a second frequency into downsampled clocks having the same frequency. The apparatus may adjust a frequency of the second clock so that the downsampled clocks are phase aligned. The apparatus may reset counters of the divider circuits that perform the downsampling so align them to a counter for the first clock. A counter for the second clock may also be reset to align with the counter for the first clock. The synchronized clocks may be applied in data storage operations, such as self-servo writing operations, where the first clock may be a read clock and the second clock may be a write clock.

公开(公告)号：US10803902B1

公开(公告)日：2020-10-13

申请号：US16104929

申请日：2018-08-19

Applicant: Seagate Technology LLC

Inventor： Zheng Wu ,  Marcus Marrow ,  Jason Bellorado

IPC: G06F3/00 ,  G11B20/10 ,  G06F3/06

Abstract: Systems and methods are disclosed for hardware-based read sample averaging in a data storage device. In one example, a read channel circuit including a buffer memory is configured to receive a read instruction to read a selected sector, obtain detected sample values for the selected sector, and determine whether the read instruction corresponds to a re-read operation for the selected sector based on determining whether there are stored samples for the selected sector already stored to a locked buffer entry of the buffer memory. When there are stored sample values stored to the locked buffer entry, the example read channel circuit determines the re-read operation is occurring, and performs read sample averaging based on the detected sample values and the stored sample values to produce averaged sample values. Other examples and configurations are also described.

公开(公告)号：US10607648B1

公开(公告)日：2020-03-31

申请号：US16025363

申请日：2018-07-02

Applicant: Seagate Technology LLC

Inventor： Zheng Wu ,  Marcus Marrow ,  Jason Bellorado

IPC: G11B5/09 ,  G11B20/10

Abstract: Systems and methods are disclosed for head delay calibration and tracking multi-sensor magnetic recording (MSMR) systems. In certain embodiments, an apparatus may comprise a first reader and a second reader configured to simultaneously read from a single track of a data storage medium, the first reader offset from the second reader so that the first reader and the second reader detect a same signal pattern offset in time. The apparatus may further comprise a circuit configured to determine a relative offset between the first reader and the second reader, including setting a fixed delay for a first signal from the first reader, setting a second delay for a second signal from the second reader, and adjusting the second delay to align the second signal to the first signal using a timing loop, with the first signal used as a reference signal.