公开(公告)号：US11532708B2

公开(公告)日：2022-12-20

申请号：US17334422

申请日：2021-05-28

Applicant: Tokyo Electron Limited

Inventor： Lars Liebmann ,  Jeffrey Smith ,  Daniel Chanemougame ,  Paul Gutwin

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a first field-effect transistor positioned over a substrate, a second field-effect transistor stacked over the first field-effect transistor, a third field-effect transistor stacked over the second field-effect transistor, and a fourth field-effect transistor stacked over the third field-effect transistor. A bottom gate structure is disposed around a first channel structure of the first field-effect transistor and positioned over the substrate. An intermediate gate structure is disposed over the bottom gate structure and around a second channel structure of the second field-effect transistor and a third channel structure of the third field-effect transistor. A top gate structure is disposed over the intermediate gate structure and around a fourth channel structure of the fourth field-effect transistor. An inter-level contact is formed to bypass the intermediate gate structure from a first side of the intermediate gate structure, and arranged between the bottom gate structure and the top gate structure.

公开(公告)号：US11488947B2

公开(公告)日：2022-11-01

申请号：US16847001

申请日：2020-04-13

Applicant: Tokyo Electron Limited

Inventor： Lars Liebmann ,  Jeffrey Smith ,  Daniel Chanemougame ,  Anton deVilliers

IPC: H01L27/02 ,  H01L27/06

Abstract: An integrated circuit includes an array of unit cells, each unit cell of which including field effect transistors arranged in a stack. Local interconnect structures form select conductive paths between select terminals of the field effect transistors to define cell circuitry that is confined within each unit cell. An array of contacts is disposed on an accessible surface of the unit cell, where each contact is electrically coupled to a corresponding electrical node of the cell circuitry.

公开(公告)号：US20220277957A1

公开(公告)日：2022-09-01

申请号：US17632212

申请日：2020-07-29

Applicant: Tokyo Electron Limited

Inventor： H. Jim Fulford ,  Mark I. Gardner ,  Jeffrey Smith ,  Lars Liebmann ,  Daniel Chanemougame

IPC: H01L21/02

Abstract: A method of forming transistor devices is described that includes forming a first transistor plane on a substrate, the first transistor plane including at least one layer of epitaxial film adaptable for forming channels of field effect transistors, depositing a first insulator layer on the first transistor plane, depositing a first layer of polycrystalline silicon on the first insulator layer, annealing the first layer of polycrystalline silicon using laser heating. The laser heating increases grain size of the first layer of polycrystalline silicon. The method further includes forming a second transistor plane on the first layer of polycrystalline silicon, the second transistor plane being adaptable for forming channels of field effect transistors, depositing a second insulator layer on the second transistor plane, depositing a second layer of polycrystalline silicon on the second insulator layer, and annealing the second layer of polycrystalline silicon using laser heating.

公开(公告)号：US11335599B2

公开(公告)日：2022-05-17

申请号：US16721583

申请日：2019-12-19

Applicant: Tokyo Electron Limited

Inventor： Lars Liebmann ,  Jeffrey Smith ,  Anton J. deVilliers ,  Kandabara Tapily

IPC: H01L21/768 ,  H01L23/522 ,  H01L27/118 ,  H01L21/8238 ,  H01L21/822 ,  H01L27/11

Abstract: A semiconductor device includes dielectric layers and local interconnects that are stacked over a substrate alternatively, and extend along a top surface of the substrate laterally. Sidewalls of the dielectric layers and sidewalls of the local interconnects have a staircase configuration. The local interconnects are spaced apart from each other by dielectric layers and have uncovered portions by the dielectric layers. The semiconductor device also includes conductive layers selectively positioned over the uncovered portions of the local interconnects, where sidewalls of the conductive layers and sidewalls of the local interconnects are coplanar. The semiconductor device further includes isolation caps that extend from the dielectric layers. The isolation caps are positioned along sidewalls of the conductive layers and sidewalls of the local interconnects so as to separate the conductive layers from one another.

公开(公告)号：US20220085012A1

公开(公告)日：2022-03-17

申请号：US17456225

申请日：2021-11-23

Applicant: Tokyo Electron Limited

Inventor： Lars Liebmann ,  Jeffrey Smith ,  Anton J. deVilliers ,  Kandabara Tapily

IPC: H01L27/092 ,  H01L29/423 ,  H01L23/535 ,  H01L29/417 ,  H01L23/528 ,  H01L29/08 ,  H01L21/3213 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/768 ,  H03K19/0948 ,  H01L27/02 ,  H01L29/10

Abstract: In a method of forming a semiconductor device, a plurality of transistor pairs is formed to be stacked over a substrate. The plurality of transistor pairs have a plurality of gate electrodes that are stacked over the substrate and electrically coupled to gate structures of the plurality of transistor pairs, and a plurality of source/drain (S/D) local interconnects that are stacked over the substrate and electrically coupled to source regions and drain regions of the plurality of transistor pairs. A sequence of vertical and lateral etch steps are performed to etch the plurality of the gate electrodes and the plurality of S/D local interconnects so that the plurality of the gate electrodes and the plurality of S/D local interconnects have a staircase configuration.

公开(公告)号：US11114346B2

公开(公告)日：2021-09-07

申请号：US16705485

申请日：2019-12-06

Applicant: Tokyo Electron Limited

Inventor： H. Jim Fulford ,  Mark I. Gardner ,  Jeffrey Smith ,  Lars Liebmann ,  Daniel Chanemougame

IPC: H01L21/8238 ,  H01L21/822 ,  H01L21/02 ,  H01L29/786 ,  H01L29/66 ,  H01L27/092

Abstract: A method of forming transistor devices is described that includes forming a first transistor plane on a substrate, the first transistor plane including at least one layer of epitaxial film adaptable for forming channels of field effect transistors, depositing a first insulator layer on the first transistor plane, depositing a first layer of polycrystalline silicon on the first insulator layer, annealing the first layer of polycrystalline silicon using laser heating. The laser heating increases grain size of the first layer of polycrystalline silicon. The method further includes forming a second transistor plane on the first layer of polycrystalline silicon, the second transistor plane being adaptable for forming channels of field effect transistors, depositing a second insulator layer on the second transistor plane, depositing a second layer of polycrystalline silicon on the second insulator layer, and annealing the second layer of polycrystalline silicon using laser heating.

公开(公告)号：US20200381430A1

公开(公告)日：2020-12-03

申请号：US16849630

申请日：2020-04-15

Applicant: Tokyo Electron Limited

Inventor： Lars Liebmann ,  Jeffrey Smith ,  Anton deVilliers ,  Daniel Chanemougame

IPC: H01L27/092 ,  H01L23/528 ,  H01L23/535 ,  H01L29/08 ,  H03K19/21

Abstract: A 3D IC includes a substrate having a substrate surface, a first stack of semiconductor devices stacked along a thickness direction of the substrate, and a second stack of semiconductor devices stacked along the thickness direction of the substrate and provided adjacent to the first stack in a direction along the substrate surface. Each semiconductor device of the first and second stack includes a gate and a pair of source-drain regions provided on opposite sides of the respective gate, and each gate of the first and second stack is a split gate. A gate contact is physically connected to a first split gate of a first one of the semiconductor devices. The gate contact forms at least part of a local interconnect structure that electrically connects the first semiconductor device to a second semiconductor device in the 3D IC.

公开(公告)号：US20200075592A1

公开(公告)日：2020-03-05

申请号：US16560490

申请日：2019-09-04

Applicant: Tokyo Electron Limited

Inventor： Lars Liebmann ,  Jeffrey Smith ,  Anton J. deVilliers ,  Kandabara Tapily

IPC: H01L27/092 ,  H01L29/423 ,  H01L23/535 ,  H01L29/417 ,  H01L23/528 ,  H01L29/08 ,  H01L29/10 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/768 ,  H03K19/0948 ,  H01L27/02 ,  H01L21/3213

Abstract: A semiconductor device is provided. The device includes a plurality of transistor pairs that are stacked over a substrate. Each of the plurality of transistor pairs includes a n-type transistor and a p-type transistor that are stacked over one another. The device also includes a plurality of gate electrodes that are stacked over the substrate with a staircase configuration. The plurality of gate electrodes are electrically coupled to gate structures of the plurality of transistor pairs. The device further includes a plurality of source/drain (S/D) local interconnects that are stacked over the substrate with a staircase configuration. The plurality of S/D local interconnects are electrically coupled to source regions and drain regions of the plurality of transistor pairs.

公开(公告)号：US20200075489A1

公开(公告)日：2020-03-05

申请号：US16560544

申请日：2019-09-04

Applicant: Tokyo Electron Limited

Inventor： Lars Liebmann ,  Jeffrey Smith ,  Anton J. deVilliers ,  Kandabara Tapily

IPC: H01L23/528 ,  H01L27/11 ,  H01L25/065 ,  H01L29/08

Abstract: A semiconductor device is provided. The semiconductor device includes a transistor stack having a plurality of transistor pairs that are stacked over a substrate. Each transistor pair of the plurality of transistor pairs includes a n-type transistor and a p-type transistor that are stacked over one another. The plurality of transistor pairs have a plurality of gate electrodes that are stacked over the substrate and electrically coupled to gate structures of the plurality of transistor pairs, and a plurality of source/drain (S/D) local interconnects that are stacked over the substrate and electrically coupled to source regions and drain regions of the plurality of transistor pairs. The semiconductor device further includes one or more conductive planes formed over the substrate. The one or more conductive planes are positioned adjacent to the transistor stack, span a height of the transistor stack and are electrically coupled to the transistor stack.

公开(公告)号：US12002862B2

公开(公告)日：2024-06-04

申请号：US17328289

申请日：2021-05-24

Applicant: Tokyo Electron Limited

Inventor： Lars Liebmann ,  Jeffrey Smith ,  Daniel Chanemougame ,  Paul Gutwin

IPC: H01L29/786 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H10B10/00

CPC classification number: H01L29/41733 ,  H01L27/0688 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/41783 ,  H01L29/42392 ,  H01L29/78621 ,  H10B10/125 ,  H10B10/18

Abstract: A semiconductor device includes a first device plane over a substrate. The first device plane includes a first transistor device having a first source/drain (S/D) region formed in an S/D channel. A second device plane is formed over the first device plane. The second device plane includes a second transistor device having a second gate formed in a gate channel which is adjacent to the S/D channel. A first inter-level connection is formed from the first S/D region of the first transistor device to the second gate of the second transistor device. The first inter-level connection includes a lateral offset from the S/D channel to the gate channel.