公开(公告)号：US10573649B2

公开(公告)日：2020-02-25

申请号：US15045258

申请日：2016-02-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Shih-Hsien Huang ,  Yu-Ru Yang ,  Chia-Hsun Tseng ,  Cheng-Tzung Tsai ,  Chun-Yuan Wu

IPC: H01L27/092 ,  H01L29/165 ,  H01L21/8238 ,  H01L29/10 ,  H01L21/02 ,  H01L29/737

Abstract: A semiconductor device includes a substrate, a first well formed in the substrate, a second well formed in the substrate, a first fin formed on the first well, and a second fin formed on the second well. The first well includes a first conductivity type, the second well includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. The substrate includes a first semiconductor material. The first fin and the second fin include the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is larger than a lattice constant of the first semiconductor material. The first semiconductor material in the first fin includes a first concentration, the first semiconductor material in the second fin includes a second concentration, and the second concentration is larger than the first concentration.

公开(公告)号：US10439023B2

公开(公告)日：2019-10-08

申请号：US16040319

申请日：2018-07-19

Applicant: United Microelectronics Corp.

Inventor： Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hao-Ming Lee ,  Yu-Ru Yang ,  Shih-Hsien Huang ,  Chien-Hung Chen ,  Chun-Yuan Wu ,  Cheng-Tzung Tsai

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L21/225 ,  H01L21/768

Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.

公开(公告)号：US20190266214A1

公开(公告)日：2019-08-29

申请号：US15905263

申请日：2018-02-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Ching LIAO ,  Li-Chin Wang ,  Ya-Ching Cheng ,  Chien-Hung Chen ,  Chun-Liang Hou

IPC: G06F17/15

Abstract: An analyzing method and an analyzing system for manufacturing data are provided. The analyzing method includes the following steps. A plurality of models each of which has a correlation value representing a relationship between at least one of a plurality of factors and a target parameter are provided. The models are screened according to the correlation values. A rank information and a frequency information of the factors are listed up according to the models. The factors are screened according to the rank information and the frequency information. The models are ranked and at least one of the models is selected.

公开(公告)号：US10332875B2

公开(公告)日：2019-06-25

申请号：US15591031

申请日：2017-05-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tzu-Ping Chen ,  Chien-Hung Chen

IPC: H01L29/788 ,  H01L27/06 ,  H01L21/285 ,  H01L21/311 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11541 ,  H01L27/11543

Abstract: A semiconductor device includes a semiconductor substrate, a tunnel dielectric disposed on the semiconductor substrate, a floating gate disposed on the tunnel dielectric, a control gate disposed on the floating gate, and an insulation layer disposed between the floating gate and the control gate. The semiconductor device further includes a spacer continuously distributed on the sidewall surfaces of the floating gate and the control gate, and the spacer overlaps portions of the top surface of the floating gate.

公开(公告)号：US20180286474A1

公开(公告)日：2018-10-04

申请号：US15589985

申请日：2017-05-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Meng-Ping Chuang ,  Tong-Yu Chen ,  Yu-Tse Kuo

IPC: G11C11/406 ,  G11C11/407

CPC classification number: G11C5/025 ,  G11C11/412 ,  H01L27/11 ,  H01L27/1104

Abstract: A semiconductor memory device including a memory cell having a plurality of memory cells, a first P-type well region, a second P-type well region, and an N-type well region disposed between the first P-Type well region and the second P-type well region. The semiconductor memory element defines a plurality of first regions and a plurality of second regions, each of the first regions and each of the second regions including one of the memory cells, each of the second regions further includes at least two first voltage providing contacts, and at least one second voltage providing contact, wherein the first voltage providing contacts and the second voltage providing contact are not located within each first region.

公开(公告)号：US20170104070A1

公开(公告)日：2017-04-13

申请号：US14940867

申请日：2015-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen ,  Shih-Hsien Huang ,  Yu-Ru Yang ,  Huai-Tzu Chiang ,  Hao-Ming Lee ,  Sheng-Hao Lin ,  Cheng-Tzung Tsai ,  Chun-Yuan Wu

IPC: H01L29/165 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L29/165 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device comprises a semiconductor substrate and a semiconductor fin. The semiconductor substrate has an upper surface and a recess extending downwards into the semiconductor substrate from the upper surface. The semiconductor fin is disposed in the recess and extends upwards beyond the upper surface, wherein the semiconductor fin is directly in contact with semiconductor substrate, so as to form at least one semiconductor hetero-interface on a sidewall of the recess.

公开(公告)号：US20170039311A1

公开(公告)日：2017-02-09

申请号：US14852635

申请日：2015-09-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hsien Wu ,  Chen-Hsien Hsu ,  Wei-Jen Wang ,  Chien-Fu Chen ,  Chien-Hung Chen

IPC: G06F17/50 ,  H01L27/02

CPC classification number: G06F17/5072 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/088

Abstract: A method for designing a semiconductor layout structure includes following steps. A first active feature group including at least a first active feature is received, and the first active feature includes a first channel length. A pair of first dummy features is introduced to form a first cell pattern. The first dummy features include a first dummy width. A first spacing width is defined between the first active feature group and one of the first dummy features and a third spacing width is defined between the first active feature group and the other first dummy feature. The first cell pattern includes a first cell width and a first poly pitch, and the first cell width is a multiple of the first pitch. The receiving of the first active feature group and the introducing of the first dummy features are performed in by at least a computer-aided design tool.

Abstract translation: 一种用于设计半导体布局结构的方法包括以下步骤。 接收包括至少第一活动特征的第一活动特征组，并且第一活动特征包括第一信道长度。 引入一对第一虚拟特征以形成第一细胞图案。 第一虚拟特征包括第一虚拟宽度。 在第一活动特征组和第一虚拟特征之一之间限定第一间隔宽度，并且在第一活动特征组和第二虚拟特征之间限定第三间隔宽度。 第一单元图案包括第一单元宽度和第一多段间距，并且第一单元宽度是第一间距的倍数。 至少由计算机辅助设计工具执行第一活动特征组的接收和第一虚拟特征的引入。

公开(公告)号：US20160079380A1

公开(公告)日：2016-03-17

申请号：US14488295

申请日：2014-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Yi Tseng ,  Tzu-Ping Chen ,  Chun-Lung Chang ,  Chih-Haw Lee ,  Wei-Shiang Huang ,  Chien-Hung Chen

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42368 ,  H01L21/28035 ,  H01L21/28158 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7833

Abstract: A gate structure is provided. The gate structure includes a substrate, a gate disposed on the substrate and a gate dielectric layer disposed between the substrate and the gate, wherein the gate dielectric layer is in the shape of a barbell. The barbell has a thin center connecting to two bulging ends. Part of the bulging ends extends into the gate and the substrate.

Abstract translation: 提供了栅极结构。 栅极结构包括衬底，设置在衬底上的栅极和设置在衬底和栅极之间的栅极电介质层，其中栅极电介质层为杠铃形状。 杠铃具有连接到两个凸起端的薄中心。 凸出部分的一部分延伸到栅极和衬底中。

公开(公告)号：US09245079B1

公开(公告)日：2016-01-26

申请号：US14324231

申请日：2014-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsun Huang ,  Hsi-Chang Chang ,  Chao-Yao Chiang ,  Chien-Hung Chen

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/504 ,  G06F17/5081

Abstract: A computer implemented method for performing extraction is provided in the present invention. First, a layout of a semiconductor circuit having a resistor is imported by using a computer wherein a device region is defined in the layout and the resistor is located within the device region. Next, the device region of the layout are extracted, and a compensation value of Rs (Rc) is obtained according to the extracting step. An adjustment process is performed according to Rc to obtained a refined R value.

Abstract translation: 本发明提供了一种用于执行提取的计算机实现方法。 首先，通过使用其中在布局中限定器件区域并且电阻器位于器件区域内的计算机来导入具有电阻器的半导体电路的布局。 接下来，提取布局的设备区域，并且根据提取步骤获得Rs（Rc）的补偿值。 根据Rc执行调整处理以获得精确的R值。

公开(公告)号：US09158886B1

公开(公告)日：2015-10-13

申请号：US14450299

申请日：2014-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hung Chen

IPC: H01L21/66 ,  G01R31/26 ,  G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5031 ,  G06F17/5063 ,  G06F17/5072 ,  G06F2217/78 ,  G06F2217/84

Abstract: A method of designing a fin-based transistor for power optimization includes following steps. A planar field-effect transistor (planar-FET) design including a plurality of planar semiconductor devices is received. An initial fin field-effect transistor (FinFET) design including a plurality of fin-based semiconductor devices corresponding to the planar semiconductor devices is generated. A timing analysis is performed to the initial FinFET design to recognize at least a critical path and at least a non-critical path in the initial FinFET design. The non-critical path includes at least one of the fin-based semiconductor devices. The fin-based semiconductor device on the non-critical path is adjusted and thus a refined FinFET design is generated. A current required by the refined FinFET design is lower than a current required by the initial FinFET design.

Abstract translation: 设计用于功率优化的鳍式晶体管的方法包括以下步骤。 接收包括多个平面半导体器件的平面场效应晶体管（平面FET）设计。 产生包括对应于平面半导体器件的多个鳍状半导体器件的初始鳍状场效应晶体管（FinFET）设计。 对初始FinFET设计进行时序分析，以识别初始FinFET设计中的至少一个关键路径和至少一个非关键路径。 非关键路径包括至少一个鳍式半导体器件。 调整非关键路径上的鳍状半导体器件，从而产生精细的FinFET设计。 精细FinFET设计所需的电流低于初始FinFET设计所需的电流。