公开(公告)号：US11062954B2

公开(公告)日：2021-07-13

申请号：US16807108

申请日：2020-03-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chi-Ting Wu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer around the first gate structure; transforming the first gate structure into a first metal gate; removing the first metal gate to form a first recess; and forming a dielectric layer in the first recess.

公开(公告)号：US20200295160A1

公开(公告)日：2020-09-17

申请号：US16378584

申请日：2019-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Hung Chen ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Chia-Jung Hsu ,  Yu-Hsiang Lin

IPC: H01L29/66 ,  H01L21/308 ,  H01L29/205 ,  H01L29/78

Abstract: A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.

公开(公告)号：US10607882B2

公开(公告)日：2020-03-31

申请号：US15873838

申请日：2018-01-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chi-Ting Wu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/78

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon; forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion; forming a first gate structure on the SDB structure; forming an interlayer dielectric (ILD) layer on the first gate structure; removing the first gate structure to form a first recess; and forming a dielectric layer in the first recess.

公开(公告)号：US10395991B2

公开(公告)日：2019-08-27

申请号：US15830008

申请日：2017-12-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Chun-Ya Chiu ,  Chin-Hung Chen ,  Chi-Ting Wu ,  Yu-Hsiang Lin

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/768 ,  H01L23/535 ,  H01L29/49 ,  H01L29/66

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure and a second gate structure on a substrate and an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; transforming the first gate structure into a first metal gate and the second gate structure into a second metal gate; removing part of the ILD layer between the first metal gate and the second metal gate to form a recess; forming a first spacer and a second spacer in the a recess; performing a first etching process to form a first contact hole; and performing a second etching process to extend the first contact hole into a second contact hole.

公开(公告)号：US12272693B2

公开(公告)日：2025-04-08

申请号：US17700475

申请日：2022-03-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ya Chiu ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin ,  Chien-Ting Lin ,  Chia-Jung Hsu ,  Chin-Hung Chen

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/8238

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region; forming a base on the HV region and fin-shaped structures on the LV region; forming a first insulating around the fin-shaped structures; removing the base, the first insulating layer, and part of the fin-shaped structures to form a first trench in the HV region and a second trench in the LV region; forming a second insulating layer in the first trench and the second trench; and planarizing the second insulating layer to form a first shallow trench isolation (STI) on the HV region and a second STI on the LV region.

公开(公告)号：US12211751B2

公开(公告)日：2025-01-28

申请号：US18398190

申请日：2023-12-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chi-Ting Wu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088

Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, an isolation structure on the SDB structure, a first spacer adjacent to the isolation structure, a metal gate adjacent to the isolation structure, a shallow trench isolation (STI around the fin-shaped structure, and a second isolation structure on the STI. Preferably, a top surface of the first spacer is lower than a top surface of the isolation structure and a bottom surface of the first spacer is lower than a bottom surface of the metal gate.

公开(公告)号：US20240347588A1

公开(公告)日：2024-10-17

申请号：US18196441

申请日：2023-05-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chin-Hung Chen ,  Ssu-I Fu ,  Yu-Hsiang Lin ,  Po-Kuang Hsieh ,  Jia-He Lin ,  Sheng-Yao Huang

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/76229

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a high-voltage (HV) region and a medium-voltage (MV) region, forming a first trench on the HV region, forming a second trench adjacent to the first trench and extending the first trench to form a third trench, forming a first shallow trench isolation (STI) in the second trench and a second STI in the third trench, and then forming a first gate structure between the first STI and the second STI. Preferably, a bottom surface of the second STI is lower than a bottom surface of the first STI.

公开(公告)号：US12074070B2

公开(公告)日：2024-08-27

申请号：US18209492

申请日：2023-06-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Chun-Ya Chiu ,  Chi-Ting Wu ,  Chin-Hung Chen ,  Yu-Hsiang Lin

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/823481 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649

Abstract: A semiconductor device includes a single diffusion break (SDB) structure dividing a fin-shaped structure into a first portion and a second portion, a first isolation structure on the SDB structure, a shallow trench isolation (STI) adjacent to the SDB structure, and a second isolation structure on the STI. Preferably, the first isolation structure further includes a cap layer on the SDB structure and a dielectric layer on the cap layer.

公开(公告)号：US12068309B2

公开(公告)日：2024-08-20

申请号：US17585582

申请日：2022-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin ,  Chien-Ting Lin ,  Chia-Jung Hsu ,  Chun-Ya Chiu ,  Chin-Hung Chen

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0266 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is lower than a top surface of the fin-shaped structure.

公开(公告)号：US20240088293A1

公开(公告)日：2024-03-14

申请号：US17960146

申请日：2022-10-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ya Chiu ,  Ssu-I Fu ,  Chin-Hung Chen ,  Jin-Yan Chiou ,  Wei-Chuan Tsai ,  Yu-Hsiang Lin

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L29/7847 ,  H01L21/26506 ,  H01L21/324 ,  H01L29/665

Abstract: An n-type metal oxide semiconductor transistor includes a gate structure, two source/drain regions, two amorphous portions and a silicide. The gate structure is disposed on a substrate. The two source/drain regions are disposed in the substrate and respectively located at two sides of the gate structure, wherein at least one of the source/drain regions is formed with a dislocation. The two amorphous portions are respectively disposed in the two source/drain regions. The silicide is disposed on the two source/drain regions, wherein at least one portion of the silicide overlaps the two amorphous portions.