公开(公告)号：US11749740B2

公开(公告)日：2023-09-05

申请号：US16731058

申请日：2019-12-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Bo-Rong Chen ,  Che-Hung Huang ,  Chun-Ming Chang ,  Yi-Shan Hsu ,  Chih-Tung Yeh ,  Shin-Chuan Huang ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/7783

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a first barrier layer on a substrate; forming a p-type semiconductor layer on the first barrier layer; forming a hard mask on the p-type semiconductor layer; patterning the hard mask and the p-type semiconductor layer; and forming a spacer adjacent to the hard mask and the p-type semiconductor layer.

公开(公告)号：US11695049B2

公开(公告)日：2023-07-04

申请号：US17029075

申请日：2020-09-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Tung Yeh ,  Chun-Liang Hou ,  Wen-Jung Liao ,  Chun-Ming Chang ,  Yi-Shan Hsu ,  Ruey-Chyr Lee

IPC: H01L29/417 ,  H01L29/778 ,  H01L29/66 ,  H01L29/06 ,  H01L29/40 ,  H01L29/205 ,  H01L29/20

CPC classification number: H01L29/4175 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/0684 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/401

Abstract: A high electron mobility transistor (HEMT) and method for forming the same are disclosed. The high electron mobility transistor includes a substrate, a mesa structure disposed on the substrate, a passivation layer disposed on the mesa structure, and at least a contact structure disposed in the passivation and the mesa structure. The mesa structure includes a channel layer and a barrier layer disposed on the channel layer. The contact structure includes a body portion and a plurality of protruding portions. The body portion is through the passivation layer. The protruding portions connect to a bottom surface of the body portion and through the barrier layer and a portion of the channel layer.

公开(公告)号：US11489048B2

公开(公告)日：2022-11-01

申请号：US17337415

申请日：2021-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chuan Huang ,  Chih-Tung Yeh ,  Chun-Ming Chang ,  Bo-Rong Chen ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/78 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66

Abstract: A method for forming a high-electron mobility transistor is disclosed. A substrate is provided. A buffer layer is formed over the substrate. A GaN channel layer is formed over the buffer layer. An AlGaN layer is formed over the GaN channel layer. A GaN source layer and a GaN drain layer are formed on the AlGaN layer within a source region and a drain region, respectively. A gate recess is formed in the AlGaN layer between the source region and the drain region. A p-GaN gate layer is then formed in and on the gate recess.

公开(公告)号：US20210288149A1

公开(公告)日：2021-09-16

申请号：US17337415

申请日：2021-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chuan Huang ,  Chih-Tung Yeh ,  Chun-Ming Chang ,  Bo-Rong Chen ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/205 ,  H01L29/778 ,  H01L29/423 ,  H01L29/66

Abstract: A method for forming a high-electron mobility transistor is disclosed. A substrate is provided. A buffer layer is formed over the substrate. A GaN channel layer is formed over the buffer layer. An AlGaN layer is formed over the GaN channel layer. A GaN source layer and a GaN drain layer are formed on the AlGaN layer within a source region and a drain region, respectively. A gate recess is formed in the AlGaN layer between the source region and the drain region. A p-GaN gate layer is then formed in and on the gate recess.

公开(公告)号：US11063124B2

公开(公告)日：2021-07-13

申请号：US16691616

申请日：2019-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chuan Huang ,  Chih-Tung Yeh ,  Chun-Ming Chang ,  Bo-Rong Chen ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/78 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423

Abstract: A high-electron mobility transistor includes a substrate; a buffer layer over the substrate; a GaN channel layer over the buffer layer; a AlGaN layer over the GaN channel layer; a gate recess in the AlGaN layer; a source region and a drain region on opposite sides of the gate recess; a GaN source layer and a GaN drain layer grown on the AlGaN layer within the source region and the drain region, respectively; and a p-GaN gate layer in and on the gate recess.

公开(公告)号：US20210111267A1

公开(公告)日：2021-04-15

申请号：US16666414

申请日：2019-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ming Chang ,  Che-Hung Huang ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: H01L29/66 ,  H01L29/778

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a first hard mask on the first barrier layer; removing the first hard mask and the first barrier layer to form a recess; forming a second barrier layer in the recess; and forming a p-type semiconductor layer on the second barrier layer.

公开(公告)号：US10776402B2

公开(公告)日：2020-09-15

申请号：US15820662

申请日：2017-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Chin Wang ,  Ya-Ching Cheng ,  Chien-Hung Chen ,  Chun-Liang Hou ,  Da-Ching Liao

IPC: G06F17/00 ,  G06F16/28 ,  G05B19/418

Abstract: A manufacture parameters grouping and analyzing method, and a manufacture parameters grouping and analyzing system are provided. The manufacture parameters grouping and analyzing method includes the following steps: A plurality of process factors are classified into a plurality of groups. In each of the groups, an intervening relationship between any two of the process factors is larger than a predetermined correlation value. In each of the groups, at least one representative factor is selected from each of the groups according to a plurality of outputting relationships of the process factors related to an output factor or a plurality of sample amounts of the process factors. Finally, the representative factor is used for various applications.

公开(公告)号：US10482153B2

公开(公告)日：2019-11-19

申请号：US15905263

申请日：2018-02-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Ching Liao ,  Li-Chin Wang ,  Ya-Ching Cheng ,  Chien-Hung Chen ,  Chun-Liang Hou

IPC: G06F7/06 ,  G06F17/50 ,  G06F17/15

Abstract: An analyzing method and an analyzing system for manufacturing data are provided. The analyzing method includes the following steps. A plurality of models each of which has a correlation value representing a relationship between at least one of a plurality of factors and a target parameter are provided. The models are screened according to the correlation values. A rank information and a frequency information of the factors are listed up according to the models. The factors are screened according to the rank information and the frequency information. The models are ranked and at least one of the models is selected.

公开(公告)号：US20180314773A1

公开(公告)日：2018-11-01

申请号：US15497489

申请日：2017-04-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Ching Cheng ,  Chun-Liang Hou ,  Chien-Hung Chen ,  Wen-Jung Liao ,  Min-Chin Hsieh ,  Da-Ching Liao ,  Li-Chin Wang

IPC: G06F17/50

Abstract: A method for analyzing a process output and a method for creating an equipment parameter model are provided. The method for analyzing the process output includes the following steps: A plurality of process steps are obtained. A processor obtains a step model set including a plurality of first step regression models, each of which represents a relationship between N of the process steps and a process output. The processor calculates a correlation of each of the first step regression models. The processor picks up at least two of the first step regression models to be a plurality of second step regression models whose correlations are ranked at top among the correlations of the first step regression models. The processor updates the step model set by a plurality of third step regression models, each of which represents a relationship between M of the process steps and the process output.

公开(公告)号：US09964587B2

公开(公告)日：2018-05-08

申请号：US15151748

申请日：2016-05-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Kuo Wang ,  Wen-Jung Liao ,  Chun-Liang Hou

IPC: G01R31/02 ,  G01R31/28 ,  H01L23/522 ,  H01L23/528 ,  H01L21/66

CPC classification number: G01R31/2884 ,  H01L22/14 ,  H01L22/30 ,  H01L22/34 ,  H01L23/5226 ,  H01L23/528

Abstract: A semiconductor structure includes at least two via chains. Each via chain includes at least one first conductive component, at least one second conductive component and at least one via. The first conductive component has an axis along an extending direction of the first conductive component. The via connects the first conductive component to the second conductive component. The via has a center defining a shift distance from the axis of the first conductive component. The shift distances of the via chains are different. A testing method using such a semiconductor structure includes drawing a resistance-shift distance diagram illustrating a relationship between the resistances of the via chains and the shift distances of the via chains. At least one dimensional feature is obtained from the resistance-shift distance diagram.