公开(公告)号：US20250017022A1

公开(公告)日：2025-01-09

申请号：US18888142

申请日：2024-09-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Yi-AN Shih ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.

公开(公告)号：US20240243057A1

公开(公告)日：2024-07-18

申请号：US18124591

申请日：2023-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L27/08

CPC classification number: H01L23/5223 ,  H01L21/76805 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/11 ,  H01L27/0805 ,  H01L2224/05026 ,  H01L2224/116 ,  H01L2924/19041 ,  H01L2924/30105

Abstract: An integrated circuit includes a substrate, an interconnection layer, an insulation layer, a metal bump structure, and a metal-insulator-metal capacitor. The interconnection layer is disposed above the substrate. The interconnection layer includes an interlayer dielectric layer and an interconnection structure disposed in the interlayer dielectric layer. The insulation layer is disposed on the interconnection layer, the metal bump structure is disposed on the insulation layer, and the metal-insulator-metal capacitor is disposed conformally on the metal bump structure and the insulation layer. A manufacturing method of the integrated circuit includes the following steps.
The interconnection layer is formed above the substrate. The insulation layer is formed on the interconnection layer, the metal bump structure is formed on the insulation layer, and the metal-insulator-metal capacitor is formed conformally on the metal bump structure and the insulation layer.

公开(公告)号：US20240081154A1

公开(公告)日：2024-03-07

申请号：US18504176

申请日：2023-11-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Da-Jun Lin ,  Chau-Chung Hou ,  Wei-Xin Gao

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/00 ,  H10N50/80

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.

公开(公告)号：US20240032433A1

公开(公告)日：2024-01-25

申请号：US18376820

申请日：2023-10-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Tai-Cheng Hou ,  Bin-Siang Tsai ,  Ting-An Chien

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/00 ,  H10N50/80

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a top electrode on the MTJ, a trapping layer in the top electrode for trapping hydrogen, a first inter-metal dielectric (IMD) layer on the MTJ, and a first metal interconnection in the first IMD layer and on the top electrode. Preferably, a top surface of the trapping layer is lower than a bottom surface of the first IMD layer.

公开(公告)号：US20230413690A1

公开(公告)日：2023-12-21

申请号：US18242550

申请日：2023-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Wei Su ,  Da-Jun Lin ,  Chih-Wei Chang ,  Bin-Siang Tsai ,  Ting-An Chien

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/063 ,  H10B63/00 ,  H10N70/028 ,  H10N70/041 ,  H10N70/841 ,  H10N70/8833

Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a resistance random access memory on the substrate, an upper electrode, a lower electrode and a resistance conversion layer between the upper electrode and the lower electrode, and a cap layer covering the outer side of the resistance random access memory, the cap layer has an upper half and a lower half, and the upper half and the lower half contain different stresses.

公开(公告)号：US20230260937A1

公开(公告)日：2023-08-17

申请号：US18138752

申请日：2023-04-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/45 ,  H01L2224/05124 ,  H01L2224/45147 ,  H01L2224/45464

Abstract: A method for fabricating a semiconductor device includes the steps of first forming an aluminum (Al) pad on a substrate, forming a passivation layer on the substrate and an opening exposing the Al pad, forming a cobalt (Co) layer in the opening and on the Al pad, bonding a wire onto the Co layer, and then performing a thermal treatment process to form a Co—Pd alloy on the Al pad.

公开(公告)号：US11723215B2

公开(公告)日：2023-08-08

申请号：US17106214

申请日：2020-11-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Yi-An Shih ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.

公开(公告)号：US20230157180A1

公开(公告)日：2023-05-18

申请号：US17548576

申请日：2021-12-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tai-Cheng Hou ,  Chau-Chung Hou ,  Da-Jun Lin ,  Wei-Xin Gao ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L43/02 ,  H01L27/22 ,  G11C11/16 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L43/02 ,  H01L27/222 ,  G11C11/161 ,  H01L23/5226 ,  H01L21/7684

Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a substrate, forming a first inter-metal dielectric (IMD) layer on the MTJ, removing part of the first IMD layer to form a damaged layer on the MTJ and a trench exposing the damaged layer, performing a ultraviolet (UV) curing process on the damaged layer, and then conducting a planarizing process to remove the damaged layer and part of the first IMD layer.

公开(公告)号：US11632889B2

公开(公告)日：2023-04-18

申请号：US17375021

申请日：2021-07-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Ya-Jyuan Hung ,  Chin-Chia Yang ,  Ting-An Chien

IPC: H10B63/00 ,  H10K10/50 ,  H10K10/82 ,  H10K19/00 ,  H10K71/20 ,  H10K85/20 ,  H10N70/20 ,  H10N70/00

Abstract: A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.

公开(公告)号：US11605777B2

公开(公告)日：2023-03-14

申请号：US17006923

申请日：2020-08-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Min-Hua Tsai ,  Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: An MRAM structure includes a dielectric layer. A first MRAM, a second MRAM and a third MRAM are disposed on the dielectric layer, wherein the second MRAM is disposed between the first MRAM and the third MRAM, and the second MRAM includes an MTJ. Two gaps are respectively disposed between the first MRAM and the second MRAM and between the second MRAM and the third MRAM. Two tensile stress pieces are respectively disposed in each of the two gaps. A first compressive stress layer surrounds and contacts the sidewall of the MTJ entirely. A second compressive stress layer covers the openings of each of the gaps and contacts the two tensile stress pieces.