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公开(公告)号：US20230320229A1
公开(公告)日：2023-10-05
申请号：US18195383
申请日：2023-05-10
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Tai-Cheng Hou , Wei-Xin Gao , Fu-Yu Tsai , Chin-Yang Hsieh , Chen-Yi Weng , Jing-Yin Jhang , Bin-Siang Tsai , Kun-Ju Li , Chih-Yueh Li , Chia-Lin Lu , Chun-Lung Chen , Kun-Yuan Liao , Yu-Tsung Lai , Wei-Hao Huang
IPC: H10N50/10 , H01L21/768 , H01L21/762 , H10N50/80
CPC classification number: H10N50/10 , H01L21/762 , H01L21/76802 , H10N50/80 , H10N35/01
Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and form a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.
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公开(公告)号：US11778922B2
公开(公告)日：2023-10-03
申请号：US17533003
申请日：2021-11-22
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Tai-Cheng Hou , Wei-Xin Gao , Fu-Yu Tsai , Chin-Yang Hsieh , Chen-Yi Weng , Jing-Yin Jhang , Bin-Siang Tsai , Kun-Ju Li , Chih-Yueh Li , Chia-Lin Lu , Chun-Lung Chen , Kun-Yuan Liao , Yu-Tsung Lai , Wei-Hao Huang
IPC: H01L41/47 , H10N50/10 , H01L21/768 , H01L21/762 , H10N50/80 , H10N35/01
CPC classification number: H10N50/10 , H01L21/762 , H01L21/76802 , H10N50/80 , H10N35/01
Abstract: A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.
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公开(公告)号：US20220238800A1
公开(公告)日：2022-07-28
申请号：US17180876
申请日：2021-02-22
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Tai-Cheng Hou , Fu-Yu Tsai , Bin-Siang Tsai , Da-Jun Lin , Chau-Chung Hou , Wei-Xin Gao
Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.
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公开(公告)号：US20250008842A1
公开(公告)日：2025-01-02
申请号：US18885729
申请日：2024-09-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Tai-Cheng Hou , Fu-Yu Tsai , Bin-Siang Tsai , Da-Jun Lin , Chau-Chung Hou , Wei-Xin Gao
Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.
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公开(公告)号：US11871677B2
公开(公告)日：2024-01-09
申请号：US17180876
申请日：2021-02-22
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Tai-Cheng Hou , Fu-Yu Tsai , Bin-Siang Tsai , Da-Jun Lin , Chau-Chung Hou , Wei-Xin Gao
Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.
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Patent Agency Ranking
公开(公告)号：US20210151666A1
公开(公告)日：2021-05-20
申请号：US17141194
申请日：2021-01-04
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Tai-Cheng Hou , Wei-Xin Gao , Fu-Yu Tsai , Chin-Yang Hsieh , Chen-Yi Weng , Jing-Yin Jhang , Bin-Siang Tsai , Kun-Ju Li , Chih-Yueh Li , Chia-Lin Lu , Chun-Lung Chen , Kun-Yuan Liao , Yu-Tsung Lai , Wei-Hao Huang
IPC: H01L43/08 , H01L21/768 , H01L43/02 , H01L21/762
Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.
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公开(公告)号：US12120962B2
公开(公告)日：2024-10-15
申请号：US18504176
申请日：2023-11-08
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Tai-Cheng Hou , Fu-Yu Tsai , Bin-Siang Tsai , Da-Jun Lin , Chau-Chung Hou , Wei-Xin Gao
Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a MRAM region and a logic region; forming a magnetic tunneling junction (MTJ) on the MRAM region; forming a top electrode on the MTJ; and then performing a flowable chemical vapor deposition (FCVD) process to form a first inter-metal dielectric (IMD) layer around the top electrode and the MTJ.
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公开(公告)号：US10916694B2
公开(公告)日：2021-02-09
申请号：US16255754
申请日：2019-01-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Tai-Cheng Hou , Wei-Xin Gao , Fu-Yu Tsai , Chin-Yang Hsieh , Chen-Yi Weng , Jing-Yin Jhang , Bin-Siang Tsai , Kun-Ju Li , Chih-Yueh Li , Chia-Lin Lu , Chun-Lung Chen , Kun-Yuan Liao , Yu-Tsung Lai , Wei-Hao Huang
IPC: H01L43/08 , H01L41/47 , H01L21/768 , H01L43/02 , H01L21/762
Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.
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公开(公告)号：US20200212290A1
公开(公告)日：2020-07-02
申请号：US16255754
申请日：2019-01-23
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Tai-Cheng Hou , Wei-Xin Gao , Fu-Yu Tsai , Chin-Yang Hsieh , Chen-Yi Weng , Jing-Yin Jhang , Bin-Siang Tsai , Kun-Ju Li , Chih-Yueh Li , Chia-Lin Lu , Chun-Lung Chen , Kun-Yuan Liao , Yu-Tsung Lai , Wei-Hao Huang
IPC: H01L41/47 , H01L21/762 , H01L43/02 , H01L21/768
Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.
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公开(公告)号：US20230403946A1
公开(公告)日：2023-12-14
申请号：US18239079
申请日：2023-08-28
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hui-Lin Wang , Tai-Cheng Hou , Wei-Xin Gao , Fu-Yu Tsai , Chin-Yang Hsieh , Chen-Yi Weng , Jing-Yin Jhang , Bin-Siang Tsai , Kun-Ju Li , Chih-Yueh Li , Chia-Lin Lu , Chun-Lung Chen , Kun-Yuan Laio , Yu-Tsung Lai , Wei-Hao Huang
IPC: H10N50/10 , H01L21/768 , H01L21/762 , H10N50/80
CPC classification number: H10N50/10 , H01L21/76802 , H01L21/762 , H10N50/80 , H10N35/01
Abstract: A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.
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