公开(公告)号：US20170076995A1

公开(公告)日：2017-03-16

申请号：US14880693

申请日：2015-10-12

Applicant: United Microelectronics Corp.

Inventor： Yun-Tzu Chang ,  Shih-Min Chou ,  Kuo-Chih Lai ,  Ching-Yun Chang ,  Hsiang-Chieh Yen ,  Yen-Chen Chen ,  Yang-Ju Lu ,  Nien-Ting Ho ,  Chi-Mao Hsu

IPC: H01L21/8238

CPC classification number: H01L21/823842

Abstract: A method for modulating a work function of a semiconductor device having a metal gate structure including the following steps is provided. A first stacked gate structure and a second stacked gate structure having an identical structure are provided on a substrate. The first stacked gate structure and the second stacked gate structure respectively include a first work function metal layer of a first type. A patterned hard mask layer is formed. The patterned hard mask layer exposes the first work function metal layer of the first stacked gate structure and covers the first work function metal layer of the second stacked gate structure. A first gas treatment is performed to the first work function metal layer of the first stacked gate structure exposed by the patterned hard mask layer. A gas used in the first gas treatment includes nitrogen-containing gas or oxygen-containing gas.

Abstract translation: 提供了一种用于调制具有包括以下步骤的金属栅极结构的半导体器件的功函数的方法。 在基板上设置具有相同结构的第一堆叠栅极结构和第二堆叠栅极结构。 第一堆叠栅极结构和第二堆叠栅极结构分别包括第一类型的第一功函数金属层。 形成图案化的硬掩模层。 图案化的硬掩模层暴露第一堆叠栅极结构的第一功函数金属层并且覆盖第二堆叠栅极结构的第一功函数金属层。 对由图案化的硬掩模层暴露的第一堆叠栅极结构的第一功函数金属层进行第一气体处理。 在第一气体处理中使用的气体包括含氮气体或含氧气体。

公开(公告)号：US20160268259A1

公开(公告)日：2016-09-15

申请号：US14683128

申请日：2015-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Yun Chang ,  Chi-Mao Hsu ,  Wei-Ming Hsiao ,  Nien-Ting Ho ,  Kuo-Chih Lai

IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/285 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L27/0922 ,  H01L21/28088 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/66545

Abstract: A semiconductor process of forming metal gates with different threshold voltages includes the following steps. A substrate having a first area and a second area is provided. A dielectric layer and a first work function layer are sequentially formed on the substrate of the first area and the second area. A second work function layer is directly formed on the first work function layer of the first area. A third work function layer is directly formed on the first work function layer of the second area, where the third work function layer is different from the second work function layer. The present invention also provides a semiconductor structure formed by said semiconductor process.

Abstract translation: 形成具有不同阈值电压的金属栅极的半导体工艺包括以下步骤。 提供具有第一区域和第二区域的衬底。 介电层和第一功函数层依次形成在第一区域和第二区域的基板上。 第二功能层直接形成在第一区域的第一功能层上。 第三功函数层直接形成在第二区域的第一功函数层上，其中第三功函数层与第二功函数层不同。 本发明还提供了由所述半导体工艺形成的半导体结构。

公开(公告)号：US09397189B2

公开(公告)日：2016-07-19

申请号：US14698828

申请日：2015-04-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Wei Chen ,  Nien-Ting Ho ,  Chien-Chung Huang ,  Chin-Fu Lin

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/263 ,  H01L29/40

CPC classification number: H01L29/4983 ,  H01L21/2633 ,  H01L21/28026 ,  H01L21/28114 ,  H01L29/401 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/7833

Abstract: A method of forming a semiconductor structure having a metal gate. Firstly, a semiconductor substrate is provided. Subsequently, at least a gate structure is formed on the semiconductor substrate. Afterwards, a spacer structure is formed to surround the gate structure. Then, an interlayer dielectric is formed. Afterwards, a planarization process is performed for the interlayer dielectric. Then, a portion of the sacrificial layer is removed to form an initial etching depth, such that an opening is formed to expose a portion of the spacer structure. The portion of the spacer structure exposed to the opening is removed so as to broaden the opening. Afterwards, remove the sacrificial layer completely via the opening. Finally, a gate conductive layer is formed to fill the opening.

公开(公告)号：US20160104786A1

公开(公告)日：2016-04-14

申请号：US14543914

申请日：2014-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Yang ,  Yu-Feng Liu ,  Jian-Cun Ke ,  Chia-Fu Hsu ,  En-Chiuan Liou ,  Ssu-I Fu ,  Chi-Mao Hsu ,  Nien-Ting Ho ,  Yu-Ru Yang ,  Yu-Ping Wang ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Yu-Ting Tseng ,  Ya-Huei Tsai ,  Chien-Chung Huang ,  Tsung-Yin Hsieh ,  Hung-Yi Wu

IPC: H01L29/49 ,  H01L27/092 ,  H01L21/28 ,  H01L21/321 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/321 ,  H01L21/823431 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/517 ,  H01L29/66545

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有层间电介质（ILD）层的衬底; 在ILD层中形成第一凹槽，第二凹槽和第三凹槽; 在所述ILD层和所述第一凹部，所述第二凹部和所述第三凹部中形成材料层; 对所述第一凹部中的所述材料层进行第一处理; 以及对所述第一凹部和所述第二凹部中的所述材料层进行第二处理。

公开(公告)号：US09305847B2

公开(公告)日：2016-04-05

申请号：US14314425

申请日：2014-06-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shin-Chi Chen ,  Chih-Yueh Li ,  Shui-Yen Lu ,  Chi-Mao Hsu ,  Yuan-Chi Pai ,  Yu-Hong Kuo ,  Nien-Ting Ho

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/311 ,  H01L29/423

CPC classification number: H01L21/82385 ,  H01L21/28026 ,  H01L21/28088 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823842 ,  H01L29/42376 ,  H01L29/66545

Abstract: A method of manufacturing a semiconductor device is provided. The method includes the following steps. A substrate including a first transistor having a first conductivity type, a second transistor having a second conductivity type and a third transistor having the first conductivity type is formed. An inner-layer dielectric layer is formed on the substrate, and includes a first gate trench corresponding to the first transistor, a second gate trench corresponding to the second transistor and a third gate trench corresponding to the third transistor. A work function metal layer is formed on the inner-layer dielectric layer. An anti-reflective layer is coated on the work function metal layer. The anti-reflective layer on the second transistor and on the top portion of the third gate trench is removed to expose the work function metal layer. The exposed work function metal layer is removed.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括以下步骤。 形成包括具有第一导电类型的第一晶体管，具有第二导电类型的第二晶体管和具有第一导电类型的第三晶体管的衬底。 内层电介质层形成在衬底上，并且包括对应于第一晶体管的第一栅极沟槽，对应于第二晶体管的第二栅极沟槽和对应于第三晶体管的第三栅极沟槽。 在内层电介质层上形成功函数金属层。 在功函数金属层上涂布抗反射层。 去除第二晶体管上的抗反射层和第三栅极沟槽的顶部以暴露功函数金属层。 暴露的功能金属层被去除。

公开(公告)号：US20140239419A1

公开(公告)日：2014-08-28

申请号：US13778227

申请日：2013-02-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Hao Chen ,  Hsin-Fu Huang ,  Chi-Yuan Sun ,  Min-Chuan Tsai ,  Wei-Yu Chen ,  Nien-Ting Ho ,  Tsun-Min Cheng ,  Chi-Mao Hsu

IPC: H01L29/423 ,  H01L29/40

CPC classification number: H01L29/401 ,  H01L21/28044 ,  H01L21/28185 ,  H01L29/4925 ,  H01L29/51

Abstract: A method of manufacturing a semiconductor device is provided. A silicon substrate is provided, and a gate insulating layer is formed on the silicon substrate. Then, a silicon barrier layer is formed on the gate insulating layer by the physical vapor deposition (PVD) process. Next, a silicon-containing layer is formed on the silicon barrier layer. The silicon barrier layer of the embodiment is a hydrogen-substantial-zero silicon layer, which has a hydrogen concentration of zero substantially.

Abstract translation: 提供一种制造半导体器件的方法。 提供硅衬底，并且在硅衬底上形成栅极绝缘层。 然后，通过物理气相沉积（PVD）工艺在栅极绝缘层上形成硅阻挡层。 接着，在硅阻隔层上形成含硅层。 本实施方式的硅阻隔层是基本上为氢的氢浓度为零的氢 - 实际为零的硅层。

公开(公告)号：US12125890B2

公开(公告)日：2024-10-22

申请号：US18226264

申请日：2023-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Wen-Yen Huang ,  Shih-Min Chou ,  Zhen Wu ,  Nien-Ting Ho ,  Chih-Chiang Wu ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/40

CPC classification number: H01L29/4966 ,  H01L27/092 ,  H01L29/401

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a first region and a second region, forming a first bottom barrier metal (BBM) layer on the first region and the second region, forming a first work function metal (WFM) layer on the first BBM layer on the first region and the second region, and then forming a diffusion barrier layer on the first WFM layer.

公开(公告)号：US20240128324A1

公开(公告)日：2024-04-18

申请号：US17990763

申请日：2022-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Shih-Min Chou ,  Nien-Ting Ho ,  Wei-Ming Hsiao ,  Li-Han Chen ,  Szu-Yao Yu ,  Chung-Yi Chiu

IPC: H01L29/16 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1606 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/4236 ,  H01L29/66045 ,  H01L29/78

Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.

公开(公告)号：US20220384603A1

公开(公告)日：2022-12-01

申请号：US17353830

申请日：2021-06-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Hsin Hsu ,  Huan-Chi Ma ,  Chien-Wen Yu ,  Shih-Min Chou ,  Nien-Ting Ho ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423

Abstract: A semiconductor device includes a substrate and a gate structure. The gate structure is disposed on the substrate, and the gate structure includes a titanium nitride barrier layer and a titanium aluminide layer. The titanium aluminide layer is disposed on the titanium nitride barrier layer, and a thickness of the titanium aluminide layer ranges from twice a thickness of the titanium nitride barrier layer to three times the thickness of the titanium nitride barrier layer.

公开(公告)号：US11322598B2

公开(公告)日：2022-05-03

申请号：US16907287

申请日：2020-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： YI-Fan Li ,  Wen-Yen Huang ,  Shih-Min Chou ,  Zhen Wu ,  Nien-Ting Ho ,  Chih-Chiang Wu ,  Ti-Bin Chen

IPC: H01L29/49 ,  H01L29/40 ,  H01L27/092

Abstract: A semiconductor device includes a substrate having a first region and a second region and a gate structure on the first region and the second region of the substrate. The gate structure includes a first bottom barrier metal (BBM) layer on the first region and the second region, a first work function metal (WFM) layer on the first region; and a diffusion barrier layer on a top surface and a sidewall of the first WFM layer on the first region and the first BBM layer on the second region. Preferably, a thickness of the first BBM layer on the second region is less than a thickness of the first BBM layer on the first region.