公开(公告)号：US12224338B2

公开(公告)日：2025-02-11

申请号：US17214932

申请日：2021-03-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Yi-Chun Chan

IPC: H01L21/31 ,  H01L21/311 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H01L29/78

Abstract: An HEMT includes a gallium nitride layer. An aluminum gallium nitride layer is disposed on the gallium nitride layer. A gate is disposed on the aluminum gallium nitride layer. The gate includes a P-type gallium nitride and a schottky contact layer. The P-type gallium nitride contacts the schottky contact layer, and a top surface of the P-type gallium nitride entirely overlaps a bottom surface of the schottky contact layer. A protective layer covers the aluminum gallium nitride layer and the gate. A source electrode is disposed at one side of the gate, penetrates the protective layer and contacts the aluminum gallium nitride layer. A drain electrode is disposed at another side of the gate, penetrates the protective layer and contacts the aluminum gallium nitride layer. A gate electrode is disposed directly on the gate, penetrates the protective layer and contacts the schottky contact layer.

公开(公告)号：US11843046B2

公开(公告)日：2023-12-12

申请号：US17145414

申请日：2021-01-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Kuan-Hung Liu

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7786 ,  H01L29/42316 ,  H01L29/452 ,  H01L29/66431 ,  H01L29/0843 ,  H01L29/66462

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer, a carrier transit layer, a carrier supply layer, a gate, a source electrode and a drain electrode. The buffer layer is on a substrate. The carrier transit layer is on the buffer layer. The carrier supply layer is on the carrier transit layer. The gate is on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the gate, wherein each of the source electrode and the drain electrode includes a conductive layer and a conductive oxide layer stacked from bottom to top.

公开(公告)号：US10431652B2

公开(公告)日：2019-10-01

申请号：US15834082

申请日：2017-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hao-Ming Lee

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L21/02 ,  H01L29/10 ,  H01L29/775 ,  B82Y10/00 ,  H01L21/324

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a single crystal substrate, a source/drain structure and a nanowire structure. The source/drain structure is disposed on and contacts with the substrate. The nanowire structure is connected to the source/drain structure.

公开(公告)号：US20180350938A1

公开(公告)日：2018-12-06

申请号：US15984426

申请日：2018-05-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Ming Lee ,  Sheng-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/4991 ,  H01L21/28088 ,  H01L29/4238 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/785

Abstract: A method for fabricating semiconductor device includes the steps of first forming a metal gate on a substrate and a spacer around the metal gate, in which the metal gate comprises a high-k dielectric layer, a work function metal layer, and a low-resistance metal layer. Next, part of the high-k dielectric layer is removed to form an air gap between the work function metal layer and the spacer.

公开(公告)号：US10008578B1

公开(公告)日：2018-06-26

申请号：US15642324

申请日：2017-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hao-Ming Lee ,  Sheng-Hao Lin ,  Hsin-Yu Chen ,  Shou-Wei Hsieh

IPC: H01L21/70 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/4991 ,  H01L21/28026 ,  H01L21/28088 ,  H01L21/28114 ,  H01L29/4238 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/785

Abstract: A method for fabricating semiconductor device includes the steps of first forming a metal gate on a substrate and a spacer around the metal gate, in which the metal gate comprises a high-k dielectric layer, a work function metal layer, and a low-resistance metal layer. Next, part of the high-k dielectric layer is removed to form an air gap between the work function metal layer and the spacer.

公开(公告)号：US20170098692A1

公开(公告)日：2017-04-06

申请号：US14936370

申请日：2015-11-09

Applicant: United Microelectronics Corp.

Inventor： Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Hao-Ming Lee ,  Yu-Ru Yang ,  Shih-Hsien Huang ,  Chien-Hung Chen ,  Chun-Yuan Wu ,  Cheng-Tzung Tsai

IPC: H01L29/06 ,  H01L21/768 ,  H01L29/66 ,  H01L21/225 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L29/0615 ,  H01L21/2253 ,  H01L21/76802 ,  H01L21/76871 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: Provided is a FinFET including a substrate, at least one fin and at least one gate. A portion of the at least one fin is embedded in the substrate. The at least one fin includes, from bottom to top, a seed layer, a stress relaxation layer and a channel layer. The at least one gate is across the at least one fin. A method of forming a FinFET is further provided.

公开(公告)号：US09502519B2

公开(公告)日：2016-11-22

申请号：US14636125

申请日：2015-03-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Sheng-Hao Lin ,  Huai-Tzu Chiang ,  Hao-Ming Lee

IPC: H01L21/336 ,  H01L29/792 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/7827

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first dielectric layer and a second dielectric layer thereon; forming a drain layer in the first dielectric layer and the second dielectric layer; forming a gate layer on the second dielectric layer; forming a channel layer in the gate layer; forming a third dielectric layer and a fourth dielectric layer on the gate layer and the channel layer; and forming a source layer in the third dielectric layer and the fourth dielectric layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有第一介电层和第二介电层的基板; 在所述第一电介质层和所述第二电介质层中形成漏极层; 在所述第二电介质层上形成栅极层; 在栅极层中形成沟道层; 在栅极层和沟道层上形成第三电介质层和第四电介质层; 以及在所述第三电介质层和所述第四电介质层中形成源极层。

公开(公告)号：US20160233303A1

公开(公告)日：2016-08-11

申请号：US14640033

申请日：2015-03-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Hao-Ming Lee ,  Sheng-Hao Lin ,  Huai-Tzu Chiang

IPC: H01L29/10 ,  H01L21/84 ,  H01L21/8234 ,  H01L29/06 ,  H01L27/088

CPC classification number: H01L29/1037 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: The present invention provides a semiconductor structure with nanowire structures. The semiconductor structure includes a substrate, more than one first source/drain disposed on the substrate, and at least one first nanowire structure disposed on the first source/drain, wherein each first source/drain and the first nanowire structure are on different levels.

Abstract translation: 本发明提供一种具有纳米线结构的半导体结构。 半导体结构包括衬底，设置在衬底上的多于一个的第一源极/漏极，以及设置在第一源极/漏极上的至少一个第一纳米线结构，其中每个第一源极/漏极和第一纳米线结构处于不同的电平。

公开(公告)号：US20160211368A1

公开(公告)日：2016-07-21

申请号：US14636125

申请日：2015-03-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Yu Chen ,  Sheng-Hao Lin ,  Huai-Tzu Chiang ,  Hao-Ming Lee

IPC: H01L29/78 ,  H01L21/311 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/42392 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/7827

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first dielectric layer and a second dielectric layer thereon; forming a drain layer in the first dielectric layer and the second dielectric layer; forming a gate layer on the second dielectric layer; forming a channel layer in the gate layer; forming a third dielectric layer and a fourth dielectric layer on the gate layer and the channel layer; and forming a source layer in the third dielectric layer and the fourth dielectric layer.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供其上具有第一介电层和第二介电层的基板; 在所述第一电介质层和所述第二电介质层中形成漏极层; 在所述第二电介质层上形成栅极层; 在栅极层中形成沟道层; 在栅极层和沟道层上形成第三电介质层和第四电介质层; 以及在所述第三电介质层和所述第四电介质层中形成源极层。

公开(公告)号：US20210134994A1

公开(公告)日：2021-05-06

申请号：US17145414

申请日：2021-01-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Huai-Tzu Chiang ,  Sheng-Hao Lin ,  Kuan-Hung Liu

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer, a carrier transit layer, a carrier supply layer, a gate, a source electrode and a drain electrode. The buffer layer is on a substrate. The carrier transit layer is on the buffer layer. The carrier supply layer is on the carrier transit layer. The gate is on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the gate, wherein each of the source electrode and the drain electrode includes a conductive layer and a conductive oxide layer stacked from bottom to top.