公开(公告)号：US20190019542A1

公开(公告)日：2019-01-17

申请号：US16005698

申请日：2018-06-12

Applicant: Winbond Electronics Corp.

Inventor： Wei-Che Chang ,  Yoshinori Tanaka

IPC: G11C7/18 ,  H01L21/762 ,  H01L21/027 ,  H01L27/105

CPC classification number: G11C7/18 ,  G11C5/02 ,  G11C8/14 ,  H01L21/027 ,  H01L21/76224 ,  H01L27/1052 ,  H01L27/10891

Abstract: Provided is a memory device including a substrate, isolation structures, conductive pillars, and bit-line structures. The substrate includes active areas. The active areas are arranged as a first array. The isolation structures are located in the substrate and extending along a Y direction. Each of the isolation structures is arranged between the active areas in adjacent two columns. The conductive pillars are located on the substrate and arranged as a second array. The conductive pillars in adjacent two rows are in contact with the active areas arranged as the same column, to form a first contact region and a second contact region. The bit-line structures are arranged on the substrate in parallel along a X direction. Each of the bit-line structures is in contact with the active areas arranged as the same column, to form a third contact region between the first and second regions.

公开(公告)号：US10083906B1

公开(公告)日：2018-09-25

申请号：US15895568

申请日：2018-02-13

Applicant: Winbond Electronics Corp.

Inventor： Kai Jen ,  Wei-Che Chang ,  Kazutaka Manabe ,  Kazuaki Takesako ,  Noriaki Ikeda ,  Yoshinori Tanaka

IPC: H01L27/108 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L23/5222 ,  H01L23/5228 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10891

Abstract: A memory device and a method for manufacturing a memory device are provided. The memory device includes a semiconductor substrate having a trench, an oxide layer formed on a surface of the trench, and a buried word line formed in the trench having the oxide layer formed thereon. The oxide layer includes a first portion extending downward from a top surface of the semiconductor substrate, a second portion extending upward from a bottom portion of the trench, and a third portion formed between and adjoining the first portion and the second portion. The third portion tapers toward the second portion. The first portion of the oxide layer is located between the buried word line and the surface of the trench.

公开(公告)号：US12089394B2

公开(公告)日：2024-09-10

申请号：US17947172

申请日：2022-09-19

Applicant: Winbond Electronics Corp.

Inventor： Chi-An Wang ,  Kai Jen ,  Wei-Che Chang

IPC: H01L23/522 ,  H10B12/00

CPC classification number: H10B12/09 ,  H10B12/0335 ,  H10B12/31 ,  H10B12/50

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate having a capacitor region and a periphery region and a capacitor. A transistor is disposed in the substrate in the capacitor region, and a conductive device is disposed in the substrate in the periphery region. The capacitor is disposed on the substrate in the capacitor region and electrically connected to the transistor, wherein an upper electrode layer of the capacitor does not extend into the periphery region.

公开(公告)号：US11765888B2

公开(公告)日：2023-09-19

申请号：US17498765

申请日：2021-10-12

Applicant: Winbond Electronics Corp.

Inventor： Yoshinori Tanaka ,  Wei-Che Chang ,  Kai Jen

IPC: H10B12/00 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/408 ,  G11C5/06

CPC classification number: H10B12/482 ,  G11C5/063 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4097 ,  H10B12/03 ,  H10B12/34 ,  H10B12/485 ,  H10B12/488

Abstract: A method of manufacturing a dynamic random access memory including the following steps is provided. A bit line is formed on a substrate. A sidewall structure is formed on a sidewall of the bit line. The sidewall structure includes a first insulation layer, a second insulation layer, and a shield conductor layer. The first insulation layer is disposed on the sidewall of the bit line. The second insulation layer is disposed on the first insulation layer. The shield conductor layer is disposed between the first insulation layer and the second insulation layer. An interconnection structure electrically connected to the shield conductor layer is formed.

公开(公告)号：US20230012828A1

公开(公告)日：2023-01-19

申请号：US17947172

申请日：2022-09-19

Applicant: Winbond Electronics Corp.

Inventor： Chi-An Wang ,  Kai Jen ,  Wei-Che Chang

IPC: H01L27/108

Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate having a capacitor region and a periphery region and a capacitor. A transistor is disposed in the substrate in the capacitor region, and a conductive device is disposed in the substrate in the periphery region. The capacitor is disposed on the substrate in the capacitor region and electrically connected to the transistor, wherein an upper electrode layer of the capacitor does not extend into the periphery region.

公开(公告)号：US20210376074A1

公开(公告)日：2021-12-02

申请号：US16885286

申请日：2020-05-28

Applicant: Winbond Electronics Corp.

Inventor： Yoshinori Tanaka ,  Wei-Che Chang

IPC: H01L29/06 ,  H01L27/092 ,  H01L21/762

Abstract: Provided is a semiconductor isolation structure including: a substrate having a first trench in a first region of the substrate and a second trench in a second region of the substrate; a filling layer is located in the first trench and the second trench; a liner layer on the sidewalls and bottom of the first trench and the second trench; a fixed negative charge layer is located between the filling layer and the liner layer in the first trench and the second trench ; and a fixed positive charge layer located between the fixed negative charge layer and the liner layer in the first trench. The liner layer, the fixed positive charge layer, the fixed negative charge layer and the filling layer in the first trench form a first isolation structure. The liner layer, the fixed negative charge layer and the filling layer in the second trench form a second isolation structure.

公开(公告)号：US11183499B2

公开(公告)日：2021-11-23

申请号：US16197380

申请日：2018-11-21

Applicant: Winbond Electronics Corp.

Inventor： Yoshinori Tanaka ,  Wei-Che Chang ,  Kai Jen

IPC: H01L27/108 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4097 ,  G11C5/06

Abstract: A dynamic random access memory (DRAM) and methods of manufacturing, writing and reading the same. The DRAM includes a substrate, a bit line, a sidewall structure and an interconnection structure. The bit line is disposed on the substrate. The sidewall structure is disposed on a sidewall of the bit line. The sidewall structure includes a first insulation layer, a second insulation layer, and a shield conductor layer. The first insulation layer is disposed on the sidewall of the bit line. The second insulation layer is disposed on the first insulation layer. The shield conductor layer is disposed between the first insulation layer and the second insulation layer. The interconnection structure is electrically connected to the shield conductor layer. The DRAM and the manufacturing, writing and reading methods thereof can effectively reduce the parasitic capacitance of the bit line.

公开(公告)号：US10910380B2

公开(公告)日：2021-02-02

申请号：US16716495

申请日：2019-12-17

Applicant: Winbond Electronics Corp.

Inventor： Kazuaki Takesako ,  Huang-Nan Chen ,  Wei-Che Chang

IPC: H01L27/108 ,  H01L23/528 ,  H01L21/762 ,  H01L21/02 ,  H01L21/311 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/285 ,  H01L21/033 ,  H01L21/027 ,  H01L21/3213

Abstract: A method of manufacturing a DRAM includes isolation structures and word line sets are formed in the substrate. A conductive material is formed on the substrate. Conductive material is removed to form first openings in the conductive material. The first openings expose surfaces of the substrate in the first areas and divide the conductive material into conductive layers, thereby the conductive layers are located on surfaces of the substrate in the second areas. A first dielectric material is filled in the first openings so as to form first dielectric layers on the substrate in the first areas. Top surfaces of the conductive layers are lower than top surfaces of the first dielectric layers. Second dielectric layers are formed respectively in the conductive layers. Capacitors are formed respectively on the conductive posts.

公开(公告)号：US10797057B2

公开(公告)日：2020-10-06

申请号：US16183506

申请日：2018-11-07

Applicant: Winbond Electronics Corp.

Inventor： Wei-Che Chang ,  Tzu-Ming Ou Yang

IPC: H01L27/108 ,  H01L21/033

Abstract: A semiconductor device and a method for manufacturing the same are provided. The method includes forming a plurality of bit line structures on a semiconductor substrate, wherein there is a plurality of trenches between the bit line structures. The method also includes forming a first oxide layer conformally covering the bit line structures and the trenches, and forming a photoresist material layer in the trenches and on the first oxide layer, wherein the photoresist material layer has an etch selectivity that is higher than that of the first oxide layer. The method further includes removing the photoresist material layer to form a plurality of capacitor contact holes between the bit line structures, and forming a capacitor contact in the capacitor contact holes.

公开(公告)号：US09972626B1

公开(公告)日：2018-05-15

申请号：US15629758

申请日：2017-06-22

Applicant: Winbond Electronics Corp.

Inventor： Kazuaki Takesako ,  Kazutaka Manabe ,  Noriaki Ikeda ,  Wei-Che Chang

IPC: H01L27/108

CPC classification number: H01L27/10808 ,  H01L27/10823 ,  H01L27/1085 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/10876

Abstract: Provided is a dynamic random access memory. A plurality of isolation structures is disposed in a substrate to define a plurality of active regions arranged along a first direction. The substrate has a trench extended along the first direction and passing through the plurality of isolation structures and the plurality of active regions. A buried word line is disposed in the trench. A plurality of gate dielectric layers is disposed in the trench of the plurality of active regions to surround and cover the buried word line. A cap layer covers the buried word line. The height of the top surface of the second side of the buried word line is lower than the height of the top surface of the first side of the buried word line passing through the plurality of active regions and the plurality of isolation structures.