公开(公告)号：US08626998B1

公开(公告)日：2014-01-07

申请号：US13972337

申请日：2013-08-21

Applicant: SMART Modular Technologies, Inc.

Inventor： Mike Hossein Amidi ,  Kelvin A. Marino ,  Satyadev Kolli

IPC: G06F12/00 ,  G11C8/00

CPC classification number: G11C8/12 ,  G11C5/04 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222

Abstract: A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller.

Abstract translation: 透明的四级存储器模块具有前侧和后侧。 前侧具有堆叠在第一存储器等级上的第三存储器级。 背面具有堆叠在第二存储器等级上的第四存储器级。 耦合到存储器模块的仿真器基于从存储器控制器接收的信号来激活并控制来自第一存储器级，第二存储器级，第三存储器级或第四存储器级的一个单独的存储器级。

公开(公告)号：US20110125966A1

公开(公告)日：2011-05-26

申请号：US12902073

申请日：2010-10-11

Applicant: Hossein Amidi ,  Kelvin A. Marino ,  Satyadev Kolli

Inventor： Hossein Amidi ,  Kelvin A. Marino ,  Satyadev Kolli

IPC: G06F12/00

CPC classification number: G11C8/12 ,  G11C5/04 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222

Abstract: A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller.

Abstract translation: 透明的四级存储器模块具有前侧和后侧。 前侧具有堆叠在第一存储器等级上的第三存储器级。 背面具有堆叠在第二存储器等级上的第四存储器级。 耦合到存储器模块的仿真器基于从存储器控制器接收的信号来激活并控制来自第一存储器级，第二存储器级，第三存储器级或第四存储器级的一个单独的存储器级。

公开(公告)号：US07660911B2

公开(公告)日：2010-02-09

申请号：US11698752

申请日：2007-01-25

Applicant: Ryan Cartland McDaniel

Inventor： Ryan Cartland McDaniel

IPC: G06F3/00

CPC classification number: G06F13/4027

Abstract: In various embodiments, options for data striping to FLASH memory are provided. In one embodiment, an apparatus is provided. The apparatus includes an SATA to ATA bridge, an ATA to USB bridge coupled to the SATA to ATA bridge, and a USB interface coupled to the ATA to USB bridge. The apparatus also includes a first FLASH memory controller coupled to the USB interface. The apparatus further includes a first FLASH memory module coupled to the first FLASH memory controller. The apparatus also includes a second FLASH memory controller coupled to the USB interface and a second FLASH memory module coupled to the second FLASH memory controller. A method for block striping data to or from a plurality of read or write channels.

Abstract translation: 在各种实施例中，提供了用于数据条带化到闪速存储器的选项。 在一个实施例中，提供了一种装置。 该装置包括SATA到ATA桥，连接到SATA到ATA桥的ATA到USB桥，以及耦合到ATA到USB桥的USB接口。 该装置还包括耦合到USB接口的第一FLASH存储器控制器。 该装置还包括耦合到第一FLASH存储器控制器的第一FLASH存储器模块。 该装置还包括耦合到USB接口的第二闪速存储器控制器和耦合到第二闪速存储器控制器的第二闪速存储器模块。 一种用于将数据分离到多个读取或写入通道的数据的方法。

公开(公告)号：US07623355B2

公开(公告)日：2009-11-24

申请号：US11075407

申请日：2005-03-07

Applicant: Grady D. Lambert ,  Ryan C. McDaniel

Inventor： Grady D. Lambert ,  Ryan C. McDaniel

IPC: H05K7/00

CPC classification number: G06F13/387

Abstract: A system, method and apparatus is provided for extended universal serial bus connectivity. In one embodiment, the invention is an apparatus. The apparatus includes a printed circuit board having a plurality or traces. The plurality of traces includes a first set of traces defining a universal serial bus. The first set of traces is routed between a connector site and an interface circuitry site. The plurality of traces also includes a second set of traces. The second set of traces defines extended signals of the universal serial bus. The second set of traces is routed between the connector site and the interface circuitry site.

Abstract translation: 提供了一种用于扩展通用串行总线连接的系统，方法和装置。 在一个实施例中，本发明是一种装置。 该装置包括具有多个或迹线的印刷电路板。 多个迹线包括限定通用串行总线的第一组轨迹。 第一组迹线在连接器站点和接口电路站点之间路由。 多个迹线还包括第二组迹线。 第二组轨迹定义了通用串行总线的扩展信号。 第二组轨迹在连接器位置和接口电路位置之间布线。

公开(公告)号：US20080002447A1

公开(公告)日：2008-01-03

申请号：US11478971

申请日：2006-06-29

Applicant: Alan Michael Gulachenski ,  Satyadev Kolli ,  Jan Hendrik Helbers

Inventor： Alan Michael Gulachenski ,  Satyadev Kolli ,  Jan Hendrik Helbers

IPC: G11C5/02

CPC classification number: G11C5/04 ,  H05K1/181 ,  H05K2201/09409 ,  H05K2203/1572 ,  Y02P70/611

Abstract: A memory supermodule containing two or more memory modules disposed on a common circuit board. Also, a memory supermodule comprising two or more memory modules, each module comprising a circuit board, the circuit boards connected by a flexible circuit. All modules in a supermodule share a single set of contact pads for establishing signal connection with a system in which the supermodule is used.

Abstract translation: 一个包含两个或多个存储器模块的存储器超模，该存储器模块设置在公共电路板上。 而且，包括两个或多个存储器模块的存储器超模块，每个模块包括电路板，电路板由柔性电路连接。 超模中的所有模块共享一组接触垫，用于与使用超模的系统建立信号连接。

公开(公告)号：US20250155941A1

公开(公告)日：2025-05-15

申请号：US18389247

申请日：2023-11-14

Applicant: SMART Modular Technologies, Inc.

Inventor： Jinying Shen ,  Torry Steed ,  Andrew Mills

IPC: G06F1/3234

Abstract: An energy source for a memory device is disclosed. In particular, a memory device such as an insertable memory card may include a detachable portion that has an energy source positioned thereon. The junction between the primary portion and the detachable portion includes sufficient conductors to convey power from the energy source as well as any needed control signals. In an exemplary aspect, the detachable portion is positioned relative to the primary portion such that the detachable portion may be readily removed while the memory device is installed in a computing device. By providing a detachable energy source, the energy source may readily be replaced in the event of failure without having to replace the entirety of the memory device. Such flexibility may save time, money, and otherwise simplify design requirements.

公开(公告)号：US20250155493A1

公开(公告)日：2025-05-15

申请号：US18389379

申请日：2023-11-14

Applicant: SMART Modular Technologies, Inc.

Inventor： Fong-Long Lin

IPC: G01R31/28 ,  G01R31/3183 ,  G01R31/319

Abstract: Systems and methods for forced early failure of cells within a memory device are disclosed. A memory device such as a dynamic random-access memory (DRAM) chip is subjected to an elevated temperature and an electric field to cause unwanted particles within the chip to migrate rapidly into the circuit elements of a memory cell, thereby causing the memory cell to fail. Subsequent testing may identify this failed cell and verify that the remaining cells within the memory device are operational. By forcing the cell to fail prior to certification testing, the end user may be reasonably confident that the certification provided for the device will remain accurate for the lifetime of the device. In contrast, without this forced early failure, such unwanted particles may migrate after deployment and may cause cell failure while deployed resulting in a botched operation.

公开(公告)号：US20240126894A1

公开(公告)日：2024-04-18

申请号：US17964663

申请日：2022-10-12

Applicant: SMART Modular Technologies, Inc.

Inventor： Victor Y. Tsai

IPC: G06F21/60 ,  G06F21/31 ,  G06F21/78

CPC classification number: G06F21/602 ,  G06F21/31 ,  G06F21/78

Abstract: Techniques for a host system or a user to verify the authenticity of a storage device or a logical sub-unit (e.g., a partition) of the storage device are disclosed. A storage device stores one or more first secret keys and a host device stores one or more second keys. A respective first secret key and a respective second key are used in a verification process that verifies the authenticity of the storage device prior to accessing the storage device.

公开(公告)号：US10755757B2

公开(公告)日：2020-08-25

申请号：US12902073

申请日：2010-10-11

Applicant: Hossein Amidi ,  Kelvin A. Marino ,  Satyadev Kolli

Inventor： Hossein Amidi ,  Kelvin A. Marino ,  Satyadev Kolli

IPC: G11C8/12 ,  G11C5/04 ,  G11C7/10 ,  G11C7/22

Abstract: A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller.

公开(公告)号：US08767463B2

公开(公告)日：2014-07-01

申请号：US13207503

申请日：2011-08-11

Applicant: Mike H. Amidi ,  Kelvin Marino

Inventor： Mike H. Amidi ,  Kelvin Marino

IPC: G11C14/00

CPC classification number: G11C14/0009

Abstract: A method of operation of a non-volatile dynamic random access memory system including: accessing a dynamic random access memory; managing a delay-locked-loop control in the dynamic random access memory; sourcing timing inputs to the dynamic random access memory by a control logic unit with the delay-locked-loop control disabled including: selecting a back-up interface through a first multiplexer and a second multiplexer, asserting an on-board termination, and accessing data in the dynamic random access memory by the control logic unit at a lower frequency; and enabling a memory control interface by the control logic unit, with the delay-locked-loop control enabled including: selecting a host interface through the first multiplexer, the second multiplexer, or a combination thereof, disabling the on-board termination, and accessing the data in the dynamic random access memory by the memory control interface at a delay-locked-loop frequency.

Abstract translation: 一种非易失性动态随机存取存储器系统的操作方法，包括：访问动态随机存取存储器; 管理动态随机存取存储器中的延迟锁定环控制; 通过禁止延迟锁定环控制的控制逻辑单元向动态随机存取存储器提供定时输入，包括：通过第一多路复用器和第二多路复用器选择备用接口，断言板载终止和访问数据 在动态随机存取存储器中由控制逻辑单元以较低的频率; 以及启用由所述控制逻辑单元进行的存储器控​​制接口，其中启用所述延迟锁定环控制，包括：通过所述第一多路复用器，所述第二多路复用器或其组合选择主机接口，禁用所述板上端接和访问 动态随机存取存储器中的数据由存储器控制接口处于延迟锁定环路频率。