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公开(公告)号：US20250155941A1
公开(公告)日：2025-05-15
申请号：US18389247
申请日：2023-11-14
Applicant: SMART Modular Technologies, Inc.
Inventor： Jinying Shen , Torry Steed , Andrew Mills
IPC: G06F1/3234
Abstract: An energy source for a memory device is disclosed. In particular, a memory device such as an insertable memory card may include a detachable portion that has an energy source positioned thereon. The junction between the primary portion and the detachable portion includes sufficient conductors to convey power from the energy source as well as any needed control signals. In an exemplary aspect, the detachable portion is positioned relative to the primary portion such that the detachable portion may be readily removed while the memory device is installed in a computing device. By providing a detachable energy source, the energy source may readily be replaced in the event of failure without having to replace the entirety of the memory device. Such flexibility may save time, money, and otherwise simplify design requirements.
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公开(公告)号：US20180095661A1
公开(公告)日：2018-04-05
申请号：US15285305
申请日：2016-10-04
Applicant: SMART Modular Technologies, Inc.
Inventor： Rajesh Ananthanarayanan , Jinying Shen , Amir Alavi
CPC classification number: G06F3/061 , G06F3/064 , G06F3/0659 , G06F3/0673
Abstract: Approaches, techniques, and mechanisms are disclosed for improving the performance of memory controllers for memory devices. A system may have a memory controller that interfaces with a memory device to store or retrieve information. When the system needs to retrieve information from the memory device, the memory controller sends an address and a command to instruct the memory device to read the information stored at the address. The memory device reads the information, and after a specific amount of time, the memory device sends the information to the memory controller. According to an embodiment, “dummy” data is sent first prior to the availability of the data read out of the memory devices, while waiting for the requested data to be accessed, and then the actual data is sent immediately following the dummy data. According to an embodiment, a geometry of a memory device has only one column of memory cells that are used to store information. The memory device with only one column in an embodiment does not require decoding of a column address. As such, the read latency of the memory device is significantly reduced.
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Patent Agency Ranking
公开(公告)号：US10510432B1
公开(公告)日：2019-12-17
申请号：US15659420
申请日：2017-07-25
Applicant: SMART Modular Technologies, Inc.
Inventor： Jinying Shen
Abstract: Approaches, techniques, and mechanisms are disclosed for a test adapter designed to improve testability of non-volatile dual in-line memory modules (NVDIMM) on automatic test equipment (ATE) testers or in-system boards, which have inadequate power supplies. An NVDIMM includes both volatile memories and non-volatile memories. A test adapter is designed to supply increased power to an NVDIMM. A test adapter is implemented using an interposer or a printed circuit board (PCB) that may be inserted into a socket on an ATE tester or on an end-user system-level board. The interposer or PCB includes a power socket for attaching a power cable to supply the external power supply to the NVDIMM. A power on/off sequence is controlled by an ATE tester to simulate or test a system power on/off sequence. An external input power is always on, but both serial and backup power signals are only on during tests of an NVDIMM.
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公开(公告)号：US20240134757A1
公开(公告)日：2024-04-25
申请号：US18400185
申请日：2023-12-29
Applicant: SMART Modular Technologies, Inc.
Inventor： Torry Steed , Kelvin Marino , Jinying Shen , Itsik Yomorta
CPC classification number: G06F11/1469 , G06F1/263 , G06F1/30 , G06F11/1451
Abstract: Systems and methods for enabling serial attached Non-Volatile (NV) memory are provided. In some embodiments, a method of operation of a computing system includes: in an NV Random Access Memory module (NVRAM) having a non-volatile device, a volatile memory device with data, a NV Controller unit (NVC), and a serial host interface, the method includes: receiving a request for data on the serial host interface and providing the requested data, from the volatile memory device, on the serial host interface. The method also includes: detecting a disruptive volatile memory event; copying the data of the volatile memory device to the NV device through the serial host interface based on the disruptive volatile memory event; and restoring the data of the volatile memory device from the NV device through the serial host interface. In this way, Dynamic Random-Access Memory (DRAM) level endurance and speed/latency can be provided while making it NV.
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公开(公告)号：US10551892B1
公开(公告)日：2020-02-04
申请号：US15709257
申请日：2017-09-19
Applicant: SMART Modular Technologies, Inc.
Inventor： Jinying Shen
IPC: G06F1/26 , G06F1/3287
Abstract: Approaches, techniques, and mechanisms are disclosed for a centralized backup power support system that improves testability of non-volatile dual in-line memory modules (NVDIMM) on Automatic Test Equipment (ATE) testers and in-system tests. An NVDIMM includes both volatile memories and non-volatile memories. According to an embodiment, a compact backup power distribution board is powered with an external power supply with an individual protection circuit. The backup power distribution board has an unlimited energy capacity for any density of NVDIMM and zero charge waiting time. According to an embodiment, instead of using an electric double-layer capacitor (EDLC) to support backup power, a resistor is used instead of an EDLC on each backup power module. There is no charging time when the backup power module does not have EDLC cells, resulting in significant reduction in test time and production cost and increase in production output.
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公开(公告)号：US10338821B2
公开(公告)日：2019-07-02
申请号：US15285305
申请日：2016-10-04
Applicant: SMART Modular Technologies, Inc.
Inventor： Rajesh Ananthanarayanan , Jinying Shen , Amir Alavi
IPC: G06F3/06
Abstract: Approaches, techniques, and mechanisms are disclosed for improving the performance of memory controllers for memory devices. A system may have a memory controller that interfaces with a memory device to store or retrieve information. When the system needs to retrieve information from the memory device, the memory controller sends an address and a command to instruct the memory device to read the information stored at the address. The memory device reads the information, and after a specific amount of time, the memory device sends the information to the memory controller. According to an embodiment, “dummy” data is sent first prior to the availability of the data read out of the memory devices, while waiting for the requested data to be accessed, and then the actual data is sent immediately following the dummy data. According to an embodiment, a geometry of a memory device has only one column of memory cells that are used to store information. The memory device with only one column in an embodiment does not require decoding of a column address. As such, the read latency of the memory device is significantly reduced.
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公开(公告)号：US09779016B1
公开(公告)日：2017-10-03
申请号：US13940118
申请日：2013-07-11
Applicant: SMART Modular Technologies, Inc.
Inventor： Jinying Shen , Robert Tower Frey , Kelvin Marino
CPC classification number: G06F12/0246 , G06F1/28 , G06F1/30 , G06F11/0754 , G06F11/1456 , G06F12/0868 , G06F2212/1016 , G06F2212/314
Abstract: An integrated circuit system, and a method of operation thereof, including: a memory unit having a volatile memory device with data and a non-volatile controller unit; a memory unit controller of the non-volatile controller unit for receiving a snoop signal for indicating an error; a non-volatile device of the memory unit for synchronously receiving data of the volatile memory device based on the snoop signal, the data autonomously copied without any intervention from outside the memory unit to prevent loss of the data; and an in-band command received by the memory unit, for autonomously restoring the data to the volatile memory device from the non-volatile device without any intervention from outside the memory unit.
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