公开(公告)号：US09505605B2

公开(公告)日：2016-11-29

申请号：US14818095

申请日：2015-08-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hua Chu ,  Chun-Wen Cheng

IPC: H01L27/14 ,  B81B3/00 ,  B81C1/00 ,  G01P15/08 ,  G01P15/125 ,  G01C19/5719

CPC classification number: B81B3/0059 ,  B81B3/0056 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/0118 ,  B81C1/00158 ,  B81C1/00714 ,  B81C2201/0112 ,  B81C2201/0132 ,  G01C19/5719 ,  G01P15/0802 ,  G01P15/125

Abstract: Methods and apparatus for forming MEMS devices. An apparatus includes at least a portion of a semiconductor substrate having a first thickness and patterned to form a moveable mass; a moving sense electrode forming the first plate of a first capacitance; at least one anchor patterned from the semiconductor substrate and having a portion that forms the second plate of the first capacitance and spaced by a first gap from the first plate; a layer of semiconductor material of a second thickness patterned to form a first electrode forming a first plate of a second capacitance and further patterned to form a second electrode overlying the at least one anchor and forming a second plate spaced by a second gap that is less than the first gap; wherein a total capacitance is formed that is the sum of the first capacitance and the second capacitance. Methods are disclosed.

公开(公告)号：US20160107880A1

公开(公告)日：2016-04-21

申请号：US14970933

申请日：2015-12-16

Applicant: FUJIFILM Corporation

Inventor： Takahiro SANO ,  Takayuki NAONO

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0072 ,  B81B2203/0127 ,  B81B2203/0353 ,  B81B2203/04 ,  B81C1/00666 ,  B81C2201/0112 ,  B81C2201/0169 ,  B81C2201/017 ,  B81C2201/0176 ,  G01C19/56 ,  G01P15/09 ,  G01P2015/084 ,  H01L41/0815 ,  H01L41/1138 ,  H01L41/319 ,  H03H9/17 ,  H03H2003/027 ,  H03H2003/0414 ,  H04R17/10 ,  H04R31/00 ,  H04R2201/003

Abstract: A producing method for a diaphragm-type resonant MEMS device includes forming a first silicon oxide film, forming a second silicon oxide film, forming a lower electrode, forming a piezoelectric film, forming an upper electrode, laminating the first silicon oxide film, the second silicon oxide film, the lower electrode, the piezoelectric film, and the upper electrode in this order on a first surface of a silicon substrate, and etching the opposite side surface of the first surface of the silicon substrate by deep reactive ion etching to form a diaphragm structure, in which the proportion R2 of the film thickness t2 of the second silicon oxide film with respect to the sum of the film thickness t1 of the first silicon oxide film and the film thickness t2 of the second silicon oxide film satisfies the following condition: 0.10 μm≦t1≦2.00 μm; and R2≧0.70.

Abstract translation: 一种膜片式谐振MEMS器件的制造方法，包括：形成第一氧化硅膜，形成第二氧化硅膜，形成下部电极，形成压电膜，形成上部电极，层叠第一氧化硅膜，第二氧化硅膜 氧化硅膜，下电极，压电膜和上电极，在硅衬底的第一表面上，并且通过深反应离子蚀刻蚀刻硅衬底的第一表面的相对侧表面，以形成 膜结构，其中第二氧化硅膜的膜厚度t2的比例R2相对于第一氧化硅膜的膜厚度t1与第二氧化硅膜的膜厚度t2之和的比例满足以下条件 ：0.10μm＆nlE; t1＆nlE;2.00μm; R2≥0.70。

公开(公告)号：US09220852B2

公开(公告)日：2015-12-29

申请号：US13856637

申请日：2013-04-04

Applicant: Klaus Kadel

Inventor： Klaus Kadel

IPC: A61M11/02 ,  B81C1/00

CPC classification number: A61M11/02 ,  B81C1/00206 ,  B81C2201/0112 ,  B81C2201/018

Abstract: In a method of producing trench-like depressions in the surface of a wafer, particularly a silicon wafer, by plasma etching, in which the depressions are produced by alternate passivation and etching, each depression in its final geometry is provided with a protective layer of the polytetrafluoroethylene type.

Abstract translation: 在通过等离子体蚀刻在晶片表面，特别是硅晶片的表面中产生沟槽状凹陷的方法中，其中通过交替的钝化和蚀刻产生凹陷，其最终几何形状中的每个凹陷设置有保护层 聚四氟乙烯型。

公开(公告)号：US20150311091A1

公开(公告)日：2015-10-29

申请号：US14646909

申请日：2013-11-01

Applicant: Beijing NMC Co., Ltd.

Inventor： Zhongwei JIANG

IPC: H01L21/3213

CPC classification number: H01L21/32137 ,  B81C1/00531 ,  B81C2201/0112 ,  B81C2201/0132 ,  H01L21/30655

Abstract: Embodiments of the invention provide a substrate etching method, which includes: a deposition operation for depositing a polymer on a side wall of a silicon groove, an etching operation for etching the side wall of the silicon groove, and repeating the deposition operation and the etching operation at least twice. In the process of completing all cycles of the etching operation, a chamber pressure of a reaction chamber is decreased from a preset highest pressure to a preset lowest pressure according to a preset rule. The substrate etching method, according to various embodiments of the invention, avoid the problem of damaging the side wall, thereby making the side wall smooth.

Abstract translation: 本发明的实施例提供了一种基板蚀刻方法，其包括：用于在硅槽的侧壁上沉积聚合物的沉积操作，用于蚀刻硅槽的侧壁的蚀刻操作，以及重复沉积操作和蚀刻 操作至少两次。 在完成蚀刻操作的所有循环的过程中，根据预设规则，反应室的室压力从预设的最高压力降低到预设的最低压力。 根据本发明的各种实施例的基板蚀刻方法避免了损坏侧壁的问题，从而使侧壁平滑。

公开(公告)号：US20150183631A1

公开(公告)日：2015-07-02

申请号：US14644937

申请日：2015-03-11

Applicant: Infineon Technologies AG

Inventor： Manfred Engelhardt ,  Martin Zgaga

IPC: B81B3/00

CPC classification number: B81B3/001 ,  B81B3/0051 ,  B81C1/00531 ,  B81C1/00626 ,  B81C2201/0112 ,  B81C2201/0132 ,  H01L21/30655

Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a micro-mechanical structure and a semiconductor material arranged over the micro-mechanical structure. A side surface of the semiconductor material includes a first region and a second region. The first region has an undulation, and the second region is a peripheral region of the side surface and decreases towards the micro-mechanical structure.

Abstract translation: 根据半导体器件的实施例，半导体器件包括布置在微机械结构上的微机械结构和半导体材料。 半导体材料的侧表面包括第一区域和第二区域。 第一区域具有起伏，第二区域是侧表面的周边区域，朝向微机械结构减小。

公开(公告)号：US20120129278A1

公开(公告)日：2012-05-24

申请号：US13387670

申请日：2011-01-25

Applicant: Manabu Yoshii ,  Kazuhiro Watanabe

Inventor： Manabu Yoshii ,  Kazuhiro Watanabe

IPC: H01L21/3065 ,  H01L21/66

CPC classification number: H01L21/30655 ,  B81C1/00087 ,  B81C2201/0112 ,  H01L21/3065

Abstract: A dry etching method includes a first step and a second step. The first step includes generating a first plasma from a gas mixture, which includes an oxidation gas and a fluorine containing gas, and performing anisotropic etching with the first plasma on a silicon layer to form a recess in the silicon layer. The second step includes alternately repeating an organic film forming process whereby an organic film is deposited on the inner surface of the recess with a second plasma, and an etching process whereby the recess covered with the organic film is anisotropically etched with the first plasma. When an etching stopper layer is exposed from a part of the bottom surface of the recess formed in the first step, the first step is switched to the second step.

Abstract translation: 干蚀刻方法包括第一步骤和第二步骤。 第一步骤包括从包括氧化气体和含氟气体的气体混合物产生第一等离子体，并且在硅层上用第一等离子体进行各向异性蚀刻，以在硅层中形成凹陷。 第二步骤包括交替地重复有机膜形成过程，其中有机膜用第二等离子体沉积在凹陷的内表面上，并且蚀刻工艺使得被有机膜覆盖的凹槽用第一等离子体各向异性蚀刻。 当蚀刻停止层从第一步骤形成的凹部的底面的一部分露出时，第一步骤切换到第二步骤。

公开(公告)号：US08012365B2

公开(公告)日：2011-09-06

申请号：US12080706

申请日：2008-04-03

Applicant: Remi Dussart ,  Philippe Lefaucheux ,  Xavier Mellhaoui ,  Lawrence John Overzet ,  Pierre Ranson ,  Thomas Tillocher ,  Mohamed Boufnichel

Inventor： Remi Dussart ,  Philippe Lefaucheux ,  Xavier Mellhaoui ,  Lawrence John Overzet ,  Pierre Ranson ,  Thomas Tillocher ,  Mohamed Boufnichel

IPC: H01L21/3065

CPC classification number: H01L21/30655 ,  B81B2203/033 ,  B81C1/00619 ,  B81C2201/0112

Abstract: A method of anisotropic plasma etching of a silicon wafer, maintained at a temperature from −40° C. to −120° C., comprising alternated and repeated steps of: etching with injection of a fluorinated gas, into the plasma reactor, and passivation with injection of silicon tetrafluoride, SiF4, and of oxygen into the plasma reactor, the flow rate of the gases in the plasma reactor being on the order of from 10% to 25% of the gas flow rate during the etch step.

Abstract translation: 保持在-40℃至-120℃的硅晶片的各向异性等离子体蚀刻的方法包括交替和重复的步骤：通过注入氟化气体进入等离子体反应器和钝化 通过将四氟化硅SiF 4和氧气注入到等离子体反应器中，等离子体反应器中的气体的流速在蚀刻步骤期间为气体流速的10％至25％。

公开(公告)号：US20090301999A1

公开(公告)日：2009-12-10

申请号：US12542659

申请日：2009-08-17

Applicant: Darrell LaRue McReynolds ,  Kia Silverbrook

Inventor： Darrell LaRue McReynolds ,  Kia Silverbrook

IPC: G11B5/127

CPC classification number: H01L21/02057 ,  B41J2/1412 ,  B41J2/1601 ,  B41J2/1623 ,  B41J2/1628 ,  B41J2/1631 ,  B41J2/164 ,  B81B2201/052 ,  B81B2203/033 ,  B81C1/00849 ,  B81C2201/0112 ,  B81C2201/0132

Abstract: A method of forming an ink supply channel for an inkjet printhead comprises the steps of: (i) providing a wafer having a frontside and a backside; (ii) etching a plurality of frontside trenches into the frontside; (iii) filling each of the trenches with a photoresist plug; (iv) forming nozzle structures on the frontside using MEMS fabrication processes; (v) etching a backside trench from the backside, the backside trench meeting with one or more of the plugs; (vi) removing a portion of each photoresist plug via the backside trench by subjecting the backside to a biased oxygen plasma etch, thereby exposing sidewall features in the backside trench; (vii) modifying the exposed sidewall features; and (viii) removing the photoresist plugs to form the ink supply channel. The ink supply channel connects the backside to the frontside.

Abstract translation: 一种形成用于喷墨打印头的供墨通道的方法包括以下步骤：（i）提供具有前侧和后侧的晶片; （ii）将多个前侧沟槽蚀刻到前侧; （iii）用光致抗蚀剂插塞填充每个沟槽; （iv）使用MEMS制造工艺在前侧形成喷嘴结构; （v）从背面蚀刻背面沟槽，所述背面沟槽与一个或多个所述插头相会合; （vi）通过使背面经受偏压的氧等离子体蚀刻，从而暴露背面沟槽中的侧壁特征，通过背侧沟槽去除每个光致抗蚀剂插塞的一部分; （vii）修改暴露的侧壁特征; 和（viii）去除光致抗蚀剂插头以形成供墨通道。 供墨通道将背面连接到前侧。

公开(公告)号：US07588693B2

公开(公告)日：2009-09-15

申请号：US11242916

申请日：2005-10-05

Applicant: Darrell LaRue McReynolds ,  Kia Silverbrook

Inventor： Darrell LaRue McReynolds ,  Kia Silverbrook

IPC: C23F1/00 ,  G01D15/00

CPC classification number: H01L21/02057 ,  B41J2/1412 ,  B41J2/1601 ,  B41J2/1623 ,  B41J2/1628 ,  B41J2/1631 ,  B41J2/164 ,  B81B2201/052 ,  B81B2203/033 ,  B81C1/00849 ,  B81C2201/0112 ,  B81C2201/0132

Abstract: A process for facilitating modification of an etched trench is provided. The process comprises: (a) providing a wafer comprising an etched trench, the trench having a photoresist plug at its base; and (b) removing a portion of the photoresist by subjecting the wafer to a biased oxygen plasma etch. The process is particularly suitable for preparing a trench for subsequent argon ion milling. Printhead integrated circuits fabricated by a process according to the invention have improved ink channel surface profiles and/or surface properties.

Abstract translation: 提供了一种便于修改蚀刻沟槽的工艺。 该方法包括：（a）提供包括蚀刻沟槽的晶片，所述沟槽在其底部具有光致抗蚀剂插塞; 和（b）通过对晶片进行偏压氧等离子体蚀刻来去除一部分光致抗蚀剂。 该方法特别适用于制备后续氩离子研磨的沟槽。 通过根据本发明的方法制造的印刷头集成电路具有改进的油墨通道表面轮廓和/或表面性质。

公开(公告)号：US07507669B2

公开(公告)日：2009-03-24

申请号：US10917168

申请日：2004-08-12

Applicant: Aaron Partridge ,  Markus Lutz

Inventor： Aaron Partridge ,  Markus Lutz

IPC: H01L21/302

CPC classification number: B81C1/00063 ,  B81B3/0086 ,  B81C2201/0112 ,  B81C2203/0136 ,  B81C2203/0145

Abstract: A device includes a top layer having at least two opposing faces, and at least two epitaxially deposited layers, each of the at least two epitaxially deposited layers situated on a respective one of the at least two opposing faces, a combined thickness of the at least two epitaxially deposited layers tuning a gap between the at least two opposing faces.

Abstract translation: 一种器件包括具有至少两个相对面的顶层和至少两个外延沉积层，所述至少两个外延沉积层中的每一个位于所述至少两个相对面中的相应一个上，所述至少两个相对面的组合厚度至少为 两个外延沉积层调整所述至少两个相对面之间的间隙。