公开(公告)号：US20150200069A1

公开(公告)日：2015-07-16

申请号：US14670671

申请日：2015-03-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Stephen E. LUCE ,  Anthony K. STAMPER

IPC: H01H59/00 ,  H01H49/00

CPC classification number: B81C1/00698 ,  B81C1/0015 ,  B81C1/00166 ,  B81C1/00523 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/0145 ,  B81C2201/0154 ,  B81C2203/0145 ,  H01H1/0036 ,  H01H1/58 ,  H01H11/00 ,  H01H49/00 ,  H01H59/00 ,  H01H59/0009 ,  H01H2059/0018 ,  Y10T29/49105

Abstract: MEMS switches and methods of manufacturing MEMS switches is provided. The MEMS switch having at least two cantilevered electrodes having ends which overlap and which are structured and operable to contact one another upon an application of a voltage by at least one fixed electrode.

Abstract translation: 提供MEMS开关和制造MEMS开关的方法。 所述MEMS开关具有至少两个悬臂电极，所述至少两个悬臂电极具有重叠的端部，并且在被至少一个固定电极施加电压时被构造和可操作以彼此接触。

公开(公告)号：US20150031161A1

公开(公告)日：2015-01-29

申请号：US14514356

申请日：2014-10-14

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jong Woon Kim ,  Won Kyu Jeung

IPC: B81C1/00

CPC classification number: B81C1/00158 ,  B81B3/0062 ,  B81B3/007 ,  B81B2201/0235 ,  B81B2203/053 ,  B81C1/00484 ,  B81C1/00531 ,  B81C1/00539 ,  B81C1/00571 ,  B81C2201/01 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/014 ,  C09K13/00 ,  C09K13/08 ,  G01C19/56 ,  G01P15/0802 ,  G01P15/0922 ,  G01P15/18 ,  G01P2015/084 ,  G01P2015/0871

Abstract: Disclosed herein an inertial sensor and a method of manufacturing the same. An inertial sensor 100 according to a preferred embodiment of the present invention is configured to include a plate-shaped membrane 110, a mass body 120 that includes an adhesive part 123 disposed under a central portion 113 of the membrane 110 and provided at the central portion thereof and a patterning part 125 provided at an outer side of the adhesive part 123 and patterned to vertically penetrate therethrough, and a first adhesive layer 130 that is formed between the membrane 110 and the adhesive part 123 and is provided at an inner side of the patterning part 125. An area of the first adhesive layer 130 is narrow by isotropic etching using the patterning part 125 as a mask, thereby making it possible to improve sensitivity of the inertial sensor 100.

Abstract translation: 本文公开了一种惯性传感器及其制造方法。 根据本发明的优选实施例的惯性传感器100被配置为包括板状膜110，质量体120，其包括设置在膜110的中心部分113下方并设置在中心部分处的粘合部123 以及设置在粘合部123的外侧并被图案化以垂直贯穿其中的图案形成部分125，以及形成在膜110和粘合部123之间的第一粘合层130，并且设置在第一粘合层130的内侧 图形部分125.通过使用图案形成部分125作为掩模的各向同性蚀刻，第一粘合剂层130的区域变窄，从而可以提高惯性传感器100的灵敏度。

公开(公告)号：US08841736B2

公开(公告)日：2014-09-23

申请号：US13960647

申请日：2013-08-06

Applicant: NXP B.V.

Inventor： Robert James Pascoe Lander

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0018 ,  B81C1/00134 ,  B81C1/00928 ,  B81C2201/0133 ,  B81C2203/0136 ,  B81C2203/0145

Abstract: An integrated circuit comprising a MEMS (microelectromechanical system) element in a plane of the integrated circuit, the MEMS element being suspended in a cavity over a substrate, said cavity including a first cavity region in said plane spatially separating an edge of the MEMS element from a wall section, said edge being arranged to be displaced relative to the wall section; and a second cavity region in said plane forming part of a fluid path further including the first cavity region, said fluid path defining a first volume; and a third cavity region in said plane defining a second volume in fluid connection with the second cavity region, wherein the maximum width of the second cavity region is larger than the maximum width of the third cavity region, the second and third cavity regions having maximum widths that are larger than the maximum width of the first cavity region.

Abstract translation: 一种集成电路，包括在所述集成电路的平面中的MEMS（微机电系统）元件，所述MEMS元件悬挂在衬底上的空腔中，所述空腔包括在所述平面中的空间上的第一空腔区域，以将所述MEMS元件的边缘与 壁部分，所述边缘被布置成相对于壁部分移位; 以及在所述平面中形成另外包括第一腔区域的流体路径的一部分的第二腔区，所述流体路径限定第一体积; 以及所述平面中的第三空腔区域，其限定与第二腔区域流体连接的第二容积，其中第二腔区域的最大宽度大于第三空腔区域的最大宽度，第二和第三空腔区域具有最大值 宽度大于第一空腔区域的最大宽度。

公开(公告)号：US08703517B2

公开(公告)日：2014-04-22

申请号：US13279409

申请日：2011-10-24

Applicant: Atsushi Taya ,  Katsuhiko Kanamori ,  Masashi Totokawa

Inventor： Atsushi Taya ,  Katsuhiko Kanamori ,  Masashi Totokawa

IPC: H01L21/02

CPC classification number: B81C1/00476 ,  B23K26/361 ,  B23K26/40 ,  B23K26/53 ,  B23K2103/50 ,  B81B2201/0264 ,  B81C2201/0133 ,  C30B29/06 ,  C30B33/04 ,  C30B33/08 ,  G01P15/0802 ,  G01P15/125 ,  H01L21/268 ,  H01L21/30608

Abstract: In a manufacturing method of a semiconductor device, a substrate including single crystalline silicon is prepared, a reformed layer that continuously extends is formed in the substrate, and the reformed layer is removed by etching. The forming the reformed layer includes polycrystallizing a portion of the single crystalline silicon by irradiating the substrate with a pulsed laser beam while moving a focal point of the laser beam in the substrate.

Abstract translation: 在半导体器件的制造方法中，制备包括单晶硅的衬底，在衬底中形成连续延伸的重整层，并且通过蚀刻去除重整层。 形成重整层包括通过在激光束的基底中移动焦点的同时用脉冲激光束照射单晶硅的一部分来多晶化。

公开(公告)号：US08691611B2

公开(公告)日：2014-04-08

申请号：US13290905

申请日：2011-11-07

Applicant: Arnim Hoechst ,  Jochen Reinmuth ,  Brett Diamond

Inventor： Arnim Hoechst ,  Jochen Reinmuth ,  Brett Diamond

IPC: H01L21/3065

CPC classification number: B81C1/00595 ,  B81B2201/0235 ,  B81B2203/0127 ,  B81B2203/0181 ,  B81B2203/053 ,  B81C2201/0112 ,  B81C2201/0133 ,  B81C2201/0136

Abstract: In a method for manufacturing a micromechanical membrane structure, a doped area is created in the front side of a silicon substrate, the depth of which doped area corresponds to the intended membrane thickness, and the lateral extent of which doped area covers at least the intended membrane surface area. In addition, in a DRIE (deep reactive ion etching) process applied to the back side of the silicon substrate, a cavity is created beneath the doped area, which DRIE process is aborted before the cavity reaches the doped area. The cavity is then deepened in a KOH etching process in which the doped substrate area functions as an etch stop, so that the doped substrate area remains as a basic membrane over the cavity.

Abstract translation: 在制造微机械膜结构的方法中，在硅衬底的前侧产生掺杂区域，其掺杂区域的深度对应于所需的膜厚度，并且其掺杂区域的横向范围至少覆盖预期的 膜表面积。 另外，在施加到硅衬底的背侧的DRIE（深反应离子蚀刻）工艺中，在掺杂区域之下产生空腔，在空腔到达掺杂区域之前DRIE工艺被中止。 然后在KOH蚀刻工艺中加深空腔，其中掺杂衬底区域用作蚀刻停止层，使得掺杂衬底区域保持为空腔上的基本膜。

公开(公告)号：US08585916B2

公开(公告)日：2013-11-19

申请号：US12812986

申请日：2009-01-21

Applicant: Thomas D. Perroud ,  Kamlesh D. Patel ,  Robert J. Meagher

Inventor： Thomas D. Perroud ,  Kamlesh D. Patel ,  Robert J. Meagher

IPC: B31D3/00

CPC classification number: G01N33/5005 ,  B01F3/0807 ,  B01F5/0471 ,  B01F13/0059 ,  B01L3/502707 ,  B01L3/502753 ,  B01L3/502761 ,  B01L3/502776 ,  B01L3/502784 ,  B01L2200/0668 ,  B01L2300/0816 ,  B01L2300/0864 ,  B01L2400/0688 ,  B81B2201/058 ,  B81C1/00047 ,  B81C1/00087 ,  B81C1/00119 ,  B81C1/00404 ,  B81C2201/0133 ,  B81C2201/0142 ,  Y10T137/9464 ,  Y10T428/24479

Abstract: Disclosed herein are methods of making micropores of a desired height and/or width between two isotropic wet etched features in a substrate which comprises single-level isotropic wet etching the two features using an etchant and a mask distance that is less than 2× a set etch depth. Also disclosed herein are methods using the micropores and microfluidic devices comprising the micropores.

Abstract translation: 本文公开的方法是在衬底中的两个各向同性湿蚀刻特征之间制造所需高度和/或宽度的微孔的方法，其包括使用蚀刻剂和小于2×一组的掩模距离的单层各向同性湿蚀刻两个特征 蚀刻深度。 本文还公开了使用包括微孔的微孔和微流体装置的方法。

公开(公告)号：US07900350B2

公开(公告)日：2011-03-08

申请号：US11373521

申请日：2006-03-10

Applicant: Taku Masai ,  Koji Sano

Inventor： Taku Masai ,  Koji Sano

IPC: H05K3/02

CPC classification number: H05K7/06 ,  B81B2207/097 ,  B81C1/00301 ,  B81C1/00571 ,  B81C2201/0133 ,  B81C2201/0142 ,  B81C2203/0109 ,  B81C2203/036 ,  H01L2924/16235 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49156

Abstract: A circuit element comprises a wiring board; the wiring board comprises a substrate and a wiring formed on the substrate, and a lid joined on the substrate containing a part of the wiring with a binder and making a sealed space above the substrate, wherein if a spot of the wiring joined with the lid by a binder is a spot of junction, a flank of both flanks of the wiring comprise bends in the spot of junction.

Abstract translation: 电路元件包括布线板; 布线板包括基板和形成在基板上的布线，以及盖子，其接合在基板上，该基板包含布线的一部分，并具有粘合剂并且在基板上方形成密封空间，其中如果布线与盖子接合的点 通过粘合剂是接合点，布线两侧的侧面包括在接合部位的弯曲部。

公开(公告)号：US07745308B2

公开(公告)日：2010-06-29

申请号：US12417114

申请日：2009-04-02

Applicant: Myung Lae Lee ,  Jong Hyun Lee ,  Sung Sik Yun ,  Dae Hun Jeong ,  Gunn Hwang ,  Chang Auck Choi ,  Chang Han Je ,  Jae Yong An

Inventor： Myung Lae Lee ,  Jong Hyun Lee ,  Sung Sik Yun ,  Dae Hun Jeong ,  Gunn Hwang ,  Chang Auck Choi ,  Chang Han Je ,  Jae Yong An

IPC: H01L21/00

CPC classification number: B81C1/00619 ,  B81C1/00626 ,  B81C2201/0132 ,  B81C2201/0133

Abstract: A method of fabricating a micro-vertical structure is provided. The method includes bonding a second crystalline silicon (Si) substrate onto a first crystalline Si substrate by interposing an insulating layer pattern and a cavity, etching the second crystalline Si substrate using a deep reactive ion etch (DRIE) process along a [111] crystal plane vertical to the second crystalline Si substrate, and etching an etched vertical surface of the second crystalline Si substrate using a crystalline wet etching process to improve the surface roughness and flatness of the etched vertical surface. As a result, no morphological defects occur on the etched vertical surface. Also, footings do not occur at an etch end-point due to the insulating layer pattern. In addition, the micro-vertical structure does not float in the air but is fixed to the first crystalline Si substrate, thereby facilitating subsequent processes.

Abstract translation: 提供一种制造微垂直结构的方法。 该方法包括通过插入绝缘层图案和空腔将第二晶体硅（Si）衬底接合到第一晶体Si衬底上，使用沿[111]晶体的深反应离子蚀刻（DRIE）工艺蚀刻第二晶体Si衬底 垂直于第二晶体Si衬底，并且使用结晶湿蚀刻工艺蚀刻第二晶体Si衬底的蚀刻垂直表面，以改善蚀刻垂直表面的表面粗糙度和平坦度。 结果，蚀刻的垂直表面上没有形成形态缺陷。 此外，由于绝缘层图案，在蚀刻终点处不发生基脚。 此外，微垂直结构不会浮在空气中，而是固定在第一晶体Si衬底上，从而有助于后续工艺。

公开(公告)号：US07741142B2

公开(公告)日：2010-06-22

申请号：US11286065

申请日：2005-11-22

Applicant: Manish Sharma

Inventor： Manish Sharma

IPC: H01L21/4763

CPC classification number: B81C1/00063 ,  B81B2201/06 ,  B81C2201/0133 ,  B81C2201/0153

Abstract: The present invention provides a method of fabricating a biosensor. The method includes providing a substrate which has a surface coating. The surface coating is deformable and the substrate includes a layered structure which has at least two electrically conductive layers separated by at least one electrically insulating layer. The method also includes imprinting a structure into the surface coating. Further, the method includes etching at least a region of the imprinted structure and the substrate to remove at least a portion of the structure and the substrate. The structure is shaped so that the etching forms at least a portion of the biosensor in the substrate and exposes at least a portion of each electrically conductive layer to form electrodes of the biosensor.

Abstract translation: 本发明提供一种制造生物传感器的方法。 该方法包括提供具有表面涂层的基底。 表面涂层是可变形的，并且衬底包括具有由至少一个电绝缘层分开的至少两个导电层的分层结构。 该方法还包括将结构压印到表面涂层中。 此外，所述方法包括蚀刻所述压印结构的至少一个区域和所述衬底以去除所述结构和所述衬底的至少一部分。 该结构被成形为使得蚀刻形成衬底中的生物传感器的至少一部分并且暴露出每个导电层的至少一部分以形成生物传感器的电极。

公开(公告)号：US07514287B2

公开(公告)日：2009-04-07

申请号：US11308303

申请日：2006-03-15

Applicant: Ter-Chang Huang ,  Hung-Yi Lin ,  Wen-Syang Hsu

Inventor： Ter-Chang Huang ,  Hung-Yi Lin ,  Wen-Syang Hsu

IPC: H01L21/00

CPC classification number: B81C1/00587 ,  B81C2201/0133

Abstract: A method for reducing dimension of an MEMS device. A single crystalline substrate having a diaphragm is provided. A first-step anisotropic dry etching process is performed to form an opening corresponding to the diaphragm in the back surface, the anisotropic dry etching stopping on a specific lattice plane extending from the edge of the diaphragm. A second-step anisotropic wet etching process is performed to etch the single crystalline substrate along the specific lattice plane until the diaphragm is exposed to form a cavity having a diamond-like shape.

Abstract translation: 一种减小MEMS器件尺寸的方法。 提供具有隔膜的单晶衬底。 执行第一步各向异性干法蚀刻工艺以形成与背面中的隔膜对应的开口，各向异性干蚀刻停止在从隔膜的边缘延伸的特定晶格面上。 执行第二步各向异性湿蚀刻工艺以沿着特定的晶格平面蚀刻单晶衬底，直到膜片暴露以形成具有菱形形状的空腔。