公开(公告)号：US06511913B1

公开(公告)日：2003-01-28

申请号：US09615142

申请日：2000-07-13

Applicant: Hubert Benzel ,  Stefan Finkbeiner

Inventor： Hubert Benzel ,  Stefan Finkbeiner

IPC: H01L2162

CPC classification number: B81C1/00158 ,  B81C2201/0136

Abstract: A method for manufacturing a membrane in which an n-doped epitaxy layer is applied on a p-doped silicon substrate. Disposed between the silicon substrate and the epitaxy layer is a p-doping which leads to a reduction of the membrane thickness during a subsequent etching process.

Abstract translation: 一种制造膜的方法，其中在p掺杂硅衬底上施加n掺杂外延层。 在硅衬底和外延层之间设置p掺杂，这导致随后的蚀刻工艺期间膜厚度的降低。

公开(公告)号：US06429458B1

公开(公告)日：2002-08-06

申请号：US09628905

申请日：2000-07-31

Applicant: Jason W. Weigold ,  Stella W. Pang

Inventor： Jason W. Weigold ,  Stella W. Pang

IPC: H01L27108

CPC classification number: B81C1/00246 ,  B81B2201/0271 ,  B81C2201/0136 ,  B81C2203/0735

Abstract: A monolithic sensor including a doped mechanical structure is movably supported by but electrically isolated from a single crystal semiconductor substrate of the sensor through a relatively simple process. The sensor is preferably made from a single crystal silicon substrate using front-side release etch-diffusion. Thick single crystal Si micromechanical devices are combined with a conventional bipolar complimentary metal oxide semiconductor (BiCMOS) integrated circuit process. This merged process allows the integration of Si mechanical resonators as thick as 15 &mgr;m thick or more with any conventional integrated circuit process with the addition of only a single masking step. The process does not require the use of Si on insulator wafers or any type of wafer bonding. The Si resonators are etched in an inductively coupled plasma source which allows deep trenches to be fabricated with high aspect ratios and smooth sidewall surfaces. Clamped-clamped beam Si resonators 500 &mgr;m long, 5 &mgr;m wide, and 11 &mgr;m thick are disclosed. A typical resonator had a resonance frequency of 28.9 kHz and an amplitude of vibration at resonance of 4.6 &mgr;m in air. Working NMOS transistors are fabricated on the same chip as the resonator with measured threshold voltages of 0.6 V and an output conductance of 2.0×10−5&OHgr;−1 for a gage voltage of 4 V.

Abstract translation: 包括掺杂机械结构的单片传感器通过相对简单的过程可移动地支撑，但是与传感器的单晶半导体衬底电隔离。 该传感器优选由使用前侧释放蚀刻扩散的单晶硅衬底制成。 厚单晶Si微机械器件与传统的双极互补金属氧化物半导体（BiCMOS）集成电路工艺相结合。 这种合并过程允许将Si机械谐振器与任何传统的集成电路过程一体化，厚度为15μm或更大，仅添加单个掩蔽步骤。 该方法不需要使用绝缘体上硅晶片或任何类型的晶片接合。 Si谐振器在电感耦合等离子体源中蚀刻，其允许以高纵横比和平滑的侧壁表面制造深沟槽。 公开了500毫米长，5微米宽和11微米厚的夹紧夹紧光束Si谐振器。 典型的谐振器的共振频率为28.9kHz，共振振幅在空气中为4.6mum。 工作的NMOS晶体管制造在与谐振器相同的芯片上，测量的阈值电压为0.6 V，输出电导率为2.0x10-5OMEGA-1，表示电压为4 V.

公开(公告)号：US06399410B1

公开(公告)日：2002-06-04

申请号：US09509448

申请日：2000-03-28

Applicant: Hitoshi Iwata ,  Makoto Murate

Inventor： Hitoshi Iwata ,  Makoto Murate

IPC: H01L2100

CPC classification number: B81C1/005 ,  B81B2201/0235 ,  B81C2201/0115 ,  B81C2201/0136 ,  G01P15/0802

Abstract: A method for anodizing silicon substrate includes forming an n-type silicon embedded layer (21) made of n-type silicon on a predetermined area of a first surface of the p-type single crystal silicon substrate (2). N-type silicon layers (4, 6) are formed on the upper surface of the p-type single crystal silicon substrate (2) and on the n-type silicon embedded layer (21). Silicon diffusion layers (5, 7) containing high-concentration p-type impurities are formed on predetermined areas of the n-type silicon layers (4, 6) to contact the n-type silicon embedded layer (21). An electrode layer (13) is formed on the lower surface of the p-type silicon substrate (2). The anode of a DC power source (15) is connected to the electrode layer (13), and the cathode is connected to a counter electrode (23), which is opposed to the p-type silicon substrate (2). A current is intensively applied to an area corresponding to an opening (21a) of the n-type silicon layer (4) in a direction from the lower surface to the upper surface of the p-type single crystal silicon substrate (2), which makes the area porous.

Abstract translation: 一种用于阳极氧化硅衬底的方法包括在p型单晶硅衬底（2）的第一表面的预定区域上形成由n型硅制成的n型硅嵌入层（21）。 在p型单晶硅衬底（2）的上表面和n型硅嵌入层（21）上形成N型硅层（4,6）。 在n型硅层（4,6）的预定区域上形成含有高浓度p型杂质的硅扩散层（5,7），以与n型硅嵌入层（21）接触。 在p型硅衬底（2）的下表面上形成电极层（13）。 直流电源（15）的阳极与电极层（13）连接，阴极与与p型硅基板（2）相对的对置电极（23）连接。 在从p型单晶硅衬底（2）的下表面到上表面的方向上，电流强烈地施加到与n型硅层（4）的开口（21a）相对应的区域， 使得该区域多孔。

公开(公告)号：US6136630A

公开(公告)日：2000-10-24

申请号：US325204

申请日：1999-06-03

Applicant: Jason W. Weigold ,  Stella W. Pang

Inventor： Jason W. Weigold ,  Stella W. Pang

IPC: B81B3/00 ,  H01L21/00

CPC classification number: B81C1/00246 ,  B81B2201/0271 ,  B81C2201/0136 ,  B81C2203/0735

Abstract: A monolithic sensor including a doped mechanical structure is movably supported by but electrically isolated from a single crystal semiconductor substrate of the sensor through a relatively simple process. The sensor is preferably made from a single crystal silicon substrate using front-side release etch-diffusion. Thick single crystal Si micromechanical devices are combined with a conventional bipolar complimentary metal oxide semiconductor (BiCMOS) integrated circuit process. This merged process allows the integration of Si mechanical resonators as thick as 15 .mu.m thick or more with any conventional integrated circuit process with the addition of only a single masking step. The process does not require the use of Si on insulator wafers or any type of wafer bonding. The Si resonators are etched in an inductively coupled plasma source which allows deep trenches to be fabricated with high aspect ratios and smooth sidewall surfaces. Clamped-clamped beam Si resonators 500 .mu.m long, 5 .mu.m wide, and 11 .mu.m thick are disclosed. A typical resonator had a resonance frequency of 28.9 kHz and an amplitude of vibration at resonance of 4.6 .mu.m in air. Working NMOS transistors are fabricated on the same chip as the resonator with measured threshold voltages of 0.6 V and an output conductance of 2.0.times.10.sup.-5 .OMEGA..sup.-1 for a gage voltage of 4 V.

Abstract translation: 包括掺杂机械结构的单片传感器通过相对简单的过程可移动地支撑，但是与传感器的单晶半导体衬底电隔离。 该传感器优选由使用前侧释放蚀刻扩散的单晶硅衬底制成。 厚单晶Si微机械器件与传统的双极互补金属氧化物半导体（BiCMOS）集成电路工艺相结合。 这种合并过程允许将Si机械谐振器与任何传统的集成电路工艺一样厚到15微米或更厚，只加上一个掩蔽步骤。 该方法不需要使用绝缘体上硅晶片或任何类型的晶片接合。 Si谐振器在电感耦合等离子体源中蚀刻，其允许以高纵横比和平滑的侧壁表面制造深沟槽。 公开了长500米，宽5微米，厚11微米的夹紧束式Si共振器。 典型的谐振器的共振频率为28.9kHz，共振振幅为4.6μm。 工作的NMOS晶体管制造在与谐振器相同的芯片上，其测量的阈值电压为0.6V，输出电导为2.0×10-5ΩEGA-1，对于量具电压为4V。

公开(公告)号：US6030850A

公开(公告)日：2000-02-29

申请号：US030414

申请日：1998-02-25

Applicant: Juergen Kurle ,  Karsten Funk ,  Franz Laermer ,  Michael Offenberg ,  Andrea Schilp

Inventor： Juergen Kurle ,  Karsten Funk ,  Franz Laermer ,  Michael Offenberg ,  Andrea Schilp

IPC: G01L1/18 ,  B81B3/00 ,  B81C1/00 ,  G01P15/08 ,  G01P15/125 ,  H01L29/84 ,  G01L1/00 ,  H01L21/461

CPC classification number: B81B7/007 ,  B81C1/0019 ,  G01P15/0802 ,  G01P15/125 ,  B81B2201/0235 ,  B81B2203/033 ,  B81C2201/0136 ,  B81C2203/0118 ,  G01P2015/0814

Abstract: In a sensor and a method for manufacturing a sensor, a movable element is patterned out of a silicon layer and is secured to a substrate. The conducting layer is subdivided into various regions, which are electrically insulated from one another. The electrical connection between the various regions of the silicon layer is established by a conducting layer, which is arranged between a first and a second insulating layer.

Abstract translation: 在传感器和制造传感器的方法中，可移动元件被图案化为硅层并固定到基底。 导电层被细分成彼此电绝缘的各个区域。 通过布置在第一和第二绝缘层之间的导电层来建立硅层的各个区域之间的电连接。

公开(公告)号：US5840597A

公开(公告)日：1998-11-24

申请号：US789515

申请日：1997-01-27

Applicant: Siegbert Hartauer

Inventor： Siegbert Hartauer

IPC: B81B3/00 ,  G01L1/18 ,  G01P15/08 ,  G01P15/12 ,  G01P15/125 ,  H01L21/00

CPC classification number: B81C1/00246 ,  G01L1/18 ,  G01P15/0802 ,  G01P15/123 ,  G01P15/125 ,  B81B2201/0235 ,  B81B2203/0109 ,  B81B2203/0315 ,  B81C2201/0136 ,  B81C2201/014 ,  B81C2203/0728 ,  B81C2203/0735

Abstract: A semiconductor device with a force and/or acceleration sensor (12), which has a spring-mass system (14, 16) responsive to the respective quantity to be measured and whose mass (16) bears via at least one resilient support element (14) on a semiconductor substrate (20). The semiconductor substrate (20) and the spring-mass system (14, 16) are integral components of a monocrystalline semiconductor crystal (10) with a IC-compatible structure. The three-dimensional structural form of the spring-mass system (12) is produced by anisotropic semiconductor etching, defined P/N junctions of the semiconductor layer arrangement functioning as etch stop means in order to more particularly create a gap (22) permitting respective movement of the mass (16) between the mass (16) and the semiconductor substrate (20).

Abstract translation: 一种具有力和/或加速度传感器（12）的半导体器件，其具有响应于待测量的相应量的弹簧质量系统（14,16），并且其质量（16）经由至少一个弹性支撑元件（ 14）在半导体衬底（20）上。 半导体衬底（20）和弹簧质量系统（14,16）是具有IC兼容结构的单晶半导体晶体（10）的组成部分。 通过各向异性半导体蚀刻制造弹簧质量体系（12）的三维结构形式，作为蚀刻停止装置的半导体层布置的限定的P / N结，以更具体地形成允许相应的间隙（22） 质量块（16）和半导体衬底（20）之间的质量块（16）的移动。

公开(公告)号：US5827756A

公开(公告)日：1998-10-27

申请号：US683274

申请日：1996-07-18

Applicant: Manabu Sugino ,  Susumu Uchikoshi ,  Takatoshi Noguchi

Inventor： Manabu Sugino ,  Susumu Uchikoshi ,  Takatoshi Noguchi

IPC: H01L29/84 ,  B81C1/00 ,  G01L9/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/00

CPC classification number: B81C1/00801 ,  B81C1/00158 ,  G01L9/0042 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81C2201/0136 ,  Y10S438/977

Abstract: A method of manufacturing a semiconductor device by which an element region for electronic circuits or the like is formed on the surface of a semiconductor substrate, a diaphragm region is formed in the bottom surface of the semiconductor substrate, and a plurality of openings having different areas and shapes are formed in the semiconductor substrate. The method includes a step of forming a first diaphragm region in the bottom surface of a semiconductor substrate, a step of partially forming a second diaphragm region in the first diaphragm region, the second diaphragm region being thinner than the first diaphragm region, and a step of forming an opening by removing part or the whole of the second diaphragm region.

Abstract translation: 一种制造半导体器件的方法，其中在半导体衬底的表面上形成用于电子电路等的元件区域，在半导体衬底的底表面中形成有隔膜区域，并且具有不同面积的多个开口 并且在半导体衬底中形成形状。 该方法包括在半导体衬底的底表面中形成第一膜片区域的步骤，在第一膜片区域中部分地形成第二膜片区域的步骤，第二膜片区域比第一膜片区域薄， 通过去除部分或全部第二隔膜区域形成开口。

公开(公告)号：US5756901A

公开(公告)日：1998-05-26

申请号：US718603

申请日：1996-09-24

Applicant: Juergen Kurle ,  Karsten Funk ,  Franz Laermer ,  Michael Offenberg ,  Andrea Schilp

Inventor： Juergen Kurle ,  Karsten Funk ,  Franz Laermer ,  Michael Offenberg ,  Andrea Schilp

IPC: G01L1/18 ,  B81B3/00 ,  B81C1/00 ,  G01P15/08 ,  G01P15/125 ,  H01L29/84 ,  G01L1/00

CPC classification number: B81B7/007 ,  B81C1/0019 ,  G01P15/0802 ,  G01P15/125 ,  B81B2201/0235 ,  B81B2203/033 ,  B81C2201/0136 ,  B81C2203/0118 ,  G01P2015/0814

Abstract: In a sensor and a method for manufacturing a sensor, a movable element is patterned out of a silicon layer and is secured to a substrate. The conducting layer is subdivided into various regions, which are electrically insulated from one another. The electrical connection between the various regions of the silicon layer is established by a conducting layer, which is arranged between a first and a second insulating layer.

Abstract translation: 在传感器和制造传感器的方法中，可移动元件被图案化为硅层并固定到基底。 导电层被细分成彼此电绝缘的各个区域。 通过布置在第一和第二绝缘层之间的导电层来建立硅层的各个区域之间的电连接。

公开(公告)号：US20160332871A1

公开(公告)日：2016-11-17

申请号：US15220267

申请日：2016-07-26

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Giuseppe Barillaro ,  Alessandro Diligenti ,  Caterina Riva ,  Roberto Campedelli ,  Stefano Losa

IPC: B81C1/00

CPC classification number: B81C1/00539 ,  B81B2201/038 ,  B81B2201/07 ,  B81B2201/12 ,  B81B2203/0118 ,  B81B2203/019 ,  B81C1/00595 ,  B81C2201/0136 ,  B81C2203/0714 ,  H01L27/10

Abstract: A process for manufacturing an interaction system of a microelectromechanical type for a storage medium, the interaction system provided with a supporting element and an interaction element carried by the supporting element, envisages the steps of: providing a wafer of semiconductor material having a substrate with a first type of conductivity and a top surface; forming a first interaction region having a second type of conductivity, opposite to the first type of conductivity, in a surface portion of the substrate in the proximity of the top surface; and carrying out an electrochemical etch of the substrate starting from the top surface, the etching being selective with respect to the second type of conductivity, so as to remove the surface portion of the substrate and separate the first interaction region from the substrate, thus forming the supporting element.

Abstract translation: 一种用于制造用于存储介质的微机电类型的相互作用系统的方法，具有支撑元件的相互作用系统和由支撑元件承载的相互作用元件，其设想是提供具有基板的半导体材料晶片，其具有 第一类导电性和顶面; 在所述顶表面附近的所述衬底的表面部分中形成具有与所述第一类型导电性相反的第二导电类型的第一相互作用区域; 并且从顶表面开始进行基板的电化学蚀刻，蚀刻相对于第二类型的导电性是选择性的，以便去除基板的表面部分并将第一相互作用区域与基板分离，从而形成 支撑元件。

公开(公告)号：US20110147864A1

公开(公告)日：2011-06-23

申请号：US12737037

申请日：2009-04-21

Applicant: Torsten Kramer ,  Marcus Ahles ,  Armin Grundmann ,  Kathrin Knese ,  Hubert Benzel ,  Gregor Schuermann ,  Simon Armbruster

Inventor： Torsten Kramer ,  Marcus Ahles ,  Armin Grundmann ,  Kathrin Knese ,  Hubert Benzel ,  Gregor Schuermann ,  Simon Armbruster

IPC: H01L21/302 ,  H01L29/84

CPC classification number: B81C1/00158 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81C2201/0115 ,  B81C2201/0136 ,  G01L9/0042

Abstract: A method for manufacturing a micromechanical diaphragm structure having access from the rear of the substrate includes: n-doping at least one contiguous lattice-type area of a p-doped silicon substrate surface; porously etching a substrate area beneath the n-doped lattice structure; producing a cavity in this substrate area beneath the n-doped lattice structure; growing a first monocrystalline silicon epitaxial layer on the n-doped lattice structure; at least one opening in the n-doped lattice structure being dimensioned in such a way that it is not closed by the growing first epitaxial layer but instead forms an access opening to the cavity; an oxide layer being created on the cavity wall; a rear access to the cavity being created, the oxide layer on the cavity wall acting as an etch stop layer; and the oxide layer being removed in the area of the cavity.

Abstract translation: 用于制造从衬底的后部进入的微机械膜结构的方法包括：n掺杂p掺杂硅衬底表面的至少一个连续的格子型区域; 在n掺杂的晶格结构下面蚀刻衬底区域; 在该n型掺杂晶格结构下面的该衬底区域中产生空腔; 在n掺杂晶格结构上生长第一单晶硅外延层; n掺杂晶格结构中的至少一个开口的尺寸设计成使得其不被生长的第一外延层闭合​​，而是形成到腔的通路口; 在空腔壁上形成氧化物层; 产生到空腔的后部通路，空腔壁上的氧化层用作蚀刻停止层; 并且在空腔的区域中去除氧化物层。