Abstract:
A method to perform performance tests on an application in a continuous deployment pipeline is provided herein. The method identifies code changes are two distinct builds in a performance test environment. The method obtains a baseline test result by executing a set of customized test scripts on a baseline build with a first code base. The method similarly tests the new build by executing the set of customized test scripts on the new build with a second code base to obtain a new test result. Performance values are determined by comparing the baseline test result and the new test result.
Abstract:
An information processing apparatus includes an external tool unit configured to provide a man-machine interface to a debugging user; and a microcontroller. The microcontroller includes: a CPU section configured to execute a program as a debugging target in a response to a first clock signal, wherein a clock rate of the first clock signal is changed in response to an instruction from the CPU section; a first transmitting section configured to transmit debugging data to the external tool unit in response to the first clock signal; a second transmitting section configured to transmit the debugging data to the external tool unit in response to a second clock signal which is different from the first clock signal; and a receiving section configured to receive data transmitted from the external tool unit.
Abstract:
An electronic circuit includes a microcontroller processor (410), a peripheral (420) coupled with the processor, an endian circuit (470) coupled with the processor and the peripheral to selectively provide different endianess modes of operation, and a detection circuit (140) to detect a failure to select a given endianess, whereby inadvertent switch of endianess due to faults is avoided. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.
Abstract:
In one embodiment, the invention comprises partial fault tolerant stream processing applications. One embodiment of a method for implementing partial fault tolerance in a stream processing application comprising a plurality of stream operators includes: defining a quality score function that expresses how well the application is performing quantitatively, injecting a fault into at least one of the plurality of operators, assessing an impact of the fault on the quality score function, and selecting at least one partial fault-tolerant technique for implementation in the application based on the quantitative metric-driven assessment.
Abstract:
A system, and in particular a system operating in real-time, may have its operation rely on a particular sequence of trigger signals, hardware or software, for proper operation. A trigger sequence checker provides a way to monitor in real-time predetermined sequences of triggers and is configured to generate an error signal upon detection of a faulty operation or sequence. Rules for sequences of triggers are stored in memory and are used by the trigger sequence checker to verify one or more sequences of triggers received as an input to the checker. A plurality of triggers may be handled by the checker. In one embodiment the checker is configurable to be set in a learning mode to capture triggers rules.
Abstract:
Certain example embodiments relate to a system for realtime detection of process execution disruptions in an event-driven architecture. A plurality of event-driven applications each execute at least one process step to participate in the execution of a process. The system includes an event bus usable by the plurality of event-driven applications to communicate events among each other. The event bus comprises a control channel, the control channel being configured to receive at least one start event and at least one stop event from the plurality of event-driven applications. The start and stop events indicate the execution of a corresponding process step. The system further includes a Complex Event Processing (CEP) engine configured to analyze the start and stop events on the control channel to detect a disruption of the process.
Abstract:
A method and system for creating uniquely representative execution path identifiers of software program. The method comprises the steps of running the software program, continuously accessing execution information of the software program, identifying execution sequences of the execution information, and creating a unique execution path identifier of each of the execution sequences by summing the execution information when the execution information is within a functional boundary thereof so as to create an execution path identifier representing a unique execution sequence of the execution information. The system comprises an execution path identification creator continuously receiving and accessing execution information of the software program, identifying execution sequences of the execution information and creating the unique execution path identifier of each of the execution sequences.
Abstract:
A system, method and computer program product for avoiding a processing flaw in a computer processor triggered by a predetermined sequence of hardware events. The system may include a detecting unit and a power-on reset unit. The detecting unit detects that the predetermined sequence of hardware events is going to occur at the computer processor. The power-on reset unit initializes the computer processor to a state stored in computer memory in response to detecting the sequence of hardware events.
Abstract:
An information processing apparatus executes a processing sequence including a plurality of processing steps. A management apparatus makes the information processing apparatus execute the processing steps in predetermined order, and thereby manages execution of the processing sequence. The management apparatus takes over execution management of the processing sequence from a first management apparatus. At this time, an information acquisition unit of the management apparatus acquires state information indicating a progress state of the processing sequence from the information processing apparatus. A control unit of the management apparatus makes the information processing apparatus continue execution of an unexecuted processing step of the processing sequence based on the state information acquired by the information acquisition unit.
Abstract:
A system, and in particular a system operating in real-time, may have its operation rely on a particular sequence of trigger signals, hardware or software, for proper operation. A trigger sequence checker provides a way to monitor in real-time predetermined sequences of triggers and is configured to generate an error signal upon detection of a faulty operation or sequence. Rules for sequences of triggers are stored in memory and are used by the trigger sequence checker to verify one or more sequences of triggers received as an input to the checker. A plurality of triggers may be handled by the checker. In one embodiment the checker is configurable to be set in a learning mode to capture triggers rules.