PERFORMANCE TESTS IN A CONTINUOUS DEPLOYMENT PIPELINE
    21.
    发明申请
    PERFORMANCE TESTS IN A CONTINUOUS DEPLOYMENT PIPELINE 有权
    连续部署管道中的性能测试

    公开(公告)号:US20150220426A1

    公开(公告)日:2015-08-06

    申请号:US14419019

    申请日:2012-08-13

    Abstract: A method to perform performance tests on an application in a continuous deployment pipeline is provided herein. The method identifies code changes are two distinct builds in a performance test environment. The method obtains a baseline test result by executing a set of customized test scripts on a baseline build with a first code base. The method similarly tests the new build by executing the set of customized test scripts on the new build with a second code base to obtain a new test result. Performance values are determined by comparing the baseline test result and the new test result.

    Abstract translation: 本文提供了在连续部署管道中对应用程序执行性能测试的方法。 该方法识别代码更改是性能测试环境中的两个不同的构建。 该方法通过在具有第一代码库的基线构建上执行一组定制的测试脚本来获得基线测试结果。 该方法类似地通过在第二代码库上执行新构建的定制测试脚本集来测试新构建,以获得新的测试结果。 性能值通过比较基准测试结果和新的测试结果来确定。

    INFORMATION PROCESSING APPARATUS WITH DEBUGGING UNIT AND DEBUGGING METHOD THEREFOR
    22.
    发明申请
    INFORMATION PROCESSING APPARATUS WITH DEBUGGING UNIT AND DEBUGGING METHOD THEREFOR 有权
    信息处理装置与调试单元及其调试方法

    公开(公告)号:US20150161019A1

    公开(公告)日:2015-06-11

    申请号:US14625814

    申请日:2015-02-19

    Inventor: Kazuya MATSUKAWA

    Abstract: An information processing apparatus includes an external tool unit configured to provide a man-machine interface to a debugging user; and a microcontroller. The microcontroller includes: a CPU section configured to execute a program as a debugging target in a response to a first clock signal, wherein a clock rate of the first clock signal is changed in response to an instruction from the CPU section; a first transmitting section configured to transmit debugging data to the external tool unit in response to the first clock signal; a second transmitting section configured to transmit the debugging data to the external tool unit in response to a second clock signal which is different from the first clock signal; and a receiving section configured to receive data transmitted from the external tool unit.

    Abstract translation: 一种信息处理设备,包括:外部工具单元,被配置为向调试用户提供人机界面; 和微控制器。 微控制器包括:CPU部分,被配置为响应于第一时钟信号执行作为调试目标的程序,其中响应于来自CPU部分的指令改变第一时钟信号的时钟速率; 第一发送部,被配置为响应于所述第一时钟信号将调试数据发送到所述外部工具单元; 第二发送部,被配置为响应于与第一时钟信号不同的第二时钟信号将调试数据发送到外部工具单元; 以及接收部,被配置为接收从所述外部工具单元发送的数据。

    Injecting a fault into a stream operator in a data stream processing application
    24.
    发明授权
    Injecting a fault into a stream operator in a data stream processing application 有权
    在数据流处理应用程序中将故障注入流操作符

    公开(公告)号:US08997039B2

    公开(公告)日:2015-03-31

    申请号:US13867595

    申请日:2013-04-22

    CPC classification number: G06F11/28 G06F11/3612 G06F11/3616

    Abstract: In one embodiment, the invention comprises partial fault tolerant stream processing applications. One embodiment of a method for implementing partial fault tolerance in a stream processing application comprising a plurality of stream operators includes: defining a quality score function that expresses how well the application is performing quantitatively, injecting a fault into at least one of the plurality of operators, assessing an impact of the fault on the quality score function, and selecting at least one partial fault-tolerant technique for implementation in the application based on the quantitative metric-driven assessment.

    Abstract translation: 在一个实施例中,本发明包括部分容错流处理应用。 用于在包括多个流操作器的流处理应用中实现部分容错的方法的一个实施例包括:定义表示应用程序在定量上执行良好的质量得分函数,将故障注入多个操作符中的至少一个 评估故障对质量得分函数的影响,以及基于定量度量驱动评估,选择至少一种部分容错技术在应用中实现。

    Real-time trigger sequence checker
    25.
    发明授权
    Real-time trigger sequence checker 有权
    实时触发序列检查器

    公开(公告)号:US08984347B2

    公开(公告)日:2015-03-17

    申请号:US13653773

    申请日:2012-10-17

    Applicant: Scaleo Chip

    CPC classification number: G06F11/28

    Abstract: A system, and in particular a system operating in real-time, may have its operation rely on a particular sequence of trigger signals, hardware or software, for proper operation. A trigger sequence checker provides a way to monitor in real-time predetermined sequences of triggers and is configured to generate an error signal upon detection of a faulty operation or sequence. Rules for sequences of triggers are stored in memory and are used by the trigger sequence checker to verify one or more sequences of triggers received as an input to the checker. A plurality of triggers may be handled by the checker. In one embodiment the checker is configurable to be set in a learning mode to capture triggers rules.

    Abstract translation: 系统,特别是实时操作的系统可以使其操作依赖于触发信号,硬件或软件的特定顺序,以进行适当的操作。 触发序列检查器提供了一种监视触发的实时预定序列的方式,并且被配置为在检测到故障操作或序列时产生错误信号。 触发序列的规则存储在存储器中,并被触发序列检查器用来验证接收到的作为输入到检验器的一个或多个触发序列。 多个触发器可以由检验器处理。 在一个实施例中,检查器可配置为设置为学习模式以捕获触发规则。

    System and method for realtime detection of process disruptions in event-driven architectures
    26.
    发明授权
    System and method for realtime detection of process disruptions in event-driven architectures 有权
    用于实时检测事件驱动体系结构中过程中断的系统和方法

    公开(公告)号:US08978049B2

    公开(公告)日:2015-03-10

    申请号:US13545474

    申请日:2012-07-10

    Applicant: Martin Grumann

    Inventor: Martin Grumann

    Abstract: Certain example embodiments relate to a system for realtime detection of process execution disruptions in an event-driven architecture. A plurality of event-driven applications each execute at least one process step to participate in the execution of a process. The system includes an event bus usable by the plurality of event-driven applications to communicate events among each other. The event bus comprises a control channel, the control channel being configured to receive at least one start event and at least one stop event from the plurality of event-driven applications. The start and stop events indicate the execution of a corresponding process step. The system further includes a Complex Event Processing (CEP) engine configured to analyze the start and stop events on the control channel to detect a disruption of the process.

    Abstract translation: 某些示例性实施例涉及用于实时检测事件驱动架构中的过程执行中断的系统。 多个事件驱动应用程序每个执行至少一个处理步骤以参与进程的执行。 该系统包括可由多个事件驱动应用程序使用的事件总线,以便彼此通信事件。 事件总线包括控制信道,控制信道被配置为从多个事件驱动应用中接收至少一个起始事件和至少一个停止事件。 启动和停止事件指示执行相应的处理步骤。 该系统还包括复杂事件处理(CEP)引擎,其被配置为分析控制信道上的起始和停止事件以检测进程的中断。

    System and method of software execution path identification
    27.
    发明授权
    System and method of software execution path identification 有权
    软件执行路径识别的系统和方法

    公开(公告)号:US08776029B2

    公开(公告)日:2014-07-08

    申请号:US13428572

    申请日:2012-03-23

    Applicant: Neil Puthuff

    Inventor: Neil Puthuff

    CPC classification number: G06F11/3612 G06F11/28 G06F11/3636

    Abstract: A method and system for creating uniquely representative execution path identifiers of software program. The method comprises the steps of running the software program, continuously accessing execution information of the software program, identifying execution sequences of the execution information, and creating a unique execution path identifier of each of the execution sequences by summing the execution information when the execution information is within a functional boundary thereof so as to create an execution path identifier representing a unique execution sequence of the execution information. The system comprises an execution path identification creator continuously receiving and accessing execution information of the software program, identifying execution sequences of the execution information and creating the unique execution path identifier of each of the execution sequences.

    Abstract translation: 一种用于创建软件程序的唯一代表执行路径标识符的方法和系统。 该方法包括以下步骤:运行软件程序,连续访问软件程序的执行信息,识别执行信息的执行顺序,以及通过在执行信息时对执行信息求和来创建每个执行序列的唯一执行路径标识符 在其功能边界内,以便创建表示执行信息的唯一执行序列的执行路径标识符。 该系统包括执行路径识别创建者,连续地接收和访问软件程序的执行信息,识别执行信息的执行顺序并创建每个执行序列的唯一执行路径标识符。

    AVOIDING PROCESSING FLAWS IN A COMPUTER PROCESSOR TRIGGERED BY A PREDETERMINED SEQUENCE OF HARDWARE EVENTS
    28.
    发明申请
    AVOIDING PROCESSING FLAWS IN A COMPUTER PROCESSOR TRIGGERED BY A PREDETERMINED SEQUENCE OF HARDWARE EVENTS 有权
    计算机处理器避免了硬件事件的预测序列触发的处理程序

    公开(公告)号:US20140164850A1

    公开(公告)日:2014-06-12

    申请号:US13708881

    申请日:2012-12-07

    Abstract: A system, method and computer program product for avoiding a processing flaw in a computer processor triggered by a predetermined sequence of hardware events. The system may include a detecting unit and a power-on reset unit. The detecting unit detects that the predetermined sequence of hardware events is going to occur at the computer processor. The power-on reset unit initializes the computer processor to a state stored in computer memory in response to detecting the sequence of hardware events.

    Abstract translation: 一种用于避免由预定的硬件事件序列触发的计算机处理器中的处理缺陷的系统,方法和计算机程序产品。 该系统可以包括检测单元和上电复位单元。 检测单元检测到计算机处理器将发生预定的硬件事件序列。 响应于检测到硬件事件的顺序,上电复位单元将计算机处理器初始化为存储在计算机存储器中的状态。

    Information processing system, management apparatus, and management method of executing a processing sequence including a plurality of processing steps
    29.
    发明授权
    Information processing system, management apparatus, and management method of executing a processing sequence including a plurality of processing steps 有权
    信息处理系统,管理装置和执行包括多个处理步骤的处理顺序的管理方法

    公开(公告)号:US08732500B2

    公开(公告)日:2014-05-20

    申请号:US13768035

    申请日:2013-02-15

    Abstract: An information processing apparatus executes a processing sequence including a plurality of processing steps. A management apparatus makes the information processing apparatus execute the processing steps in predetermined order, and thereby manages execution of the processing sequence. The management apparatus takes over execution management of the processing sequence from a first management apparatus. At this time, an information acquisition unit of the management apparatus acquires state information indicating a progress state of the processing sequence from the information processing apparatus. A control unit of the management apparatus makes the information processing apparatus continue execution of an unexecuted processing step of the processing sequence based on the state information acquired by the information acquisition unit.

    Abstract translation: 信息处理装置执行包括多个处理步骤的处理顺序。 管理装置使信息处理装置以预定顺序执行处理步骤,从而管理处理顺序的执行。 管理装置从第一管理装置接管处理顺序的执行管理。 此时,管理装置的信息获取单元从信息处理装置获取表示处理顺序的进度状态的状态信息。 管理装置的控制单元使得信息处理装置基于由信息获取单元获取的状态信息继续执行处理序列的未执行处理步骤。

    Real-Time Trigger Sequence Checker
    30.
    发明申请
    Real-Time Trigger Sequence Checker 有权
    实时触发序列检测器

    公开(公告)号:US20140108856A1

    公开(公告)日:2014-04-17

    申请号:US13653773

    申请日:2012-10-17

    Applicant: SCALEO CHIP

    CPC classification number: G06F11/28

    Abstract: A system, and in particular a system operating in real-time, may have its operation rely on a particular sequence of trigger signals, hardware or software, for proper operation. A trigger sequence checker provides a way to monitor in real-time predetermined sequences of triggers and is configured to generate an error signal upon detection of a faulty operation or sequence. Rules for sequences of triggers are stored in memory and are used by the trigger sequence checker to verify one or more sequences of triggers received as an input to the checker. A plurality of triggers may be handled by the checker. In one embodiment the checker is configurable to be set in a learning mode to capture triggers rules.

    Abstract translation: 系统,特别是实时操作的系统可以使其操作依赖于触发信号,硬件或软件的特定顺序,以进行适当的操作。 触发序列检查器提供了一种监视触发的实时预定序列的方式,并且被配置为在检测到故障操作或序列时产生错误信号。 触发序列的规则存储在存储器中,并被触发序列检查器用来验证接收到的作为输入到检验器的一个或多个触发序列。 多个触发器可以由检验器处理。 在一个实施例中,检查器可配置为设置为学习模式以捕获触发规则。

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