公开(公告)号：US11989557B2

公开(公告)日：2024-05-21

申请号：US18144569

申请日：2023-05-08

Applicant: Lodestar Licensing Group, LLC

Inventor： Qing Liang ,  Nadav Grosz

IPC: G06F12/00 ,  G06F3/06 ,  G06F9/30 ,  G06F9/48 ,  G06F12/1009

CPC classification number: G06F9/30047 ,  G06F3/0613 ,  G06F3/0617 ,  G06F3/0646 ,  G06F3/0659 ,  G06F3/0679 ,  G06F9/4806 ,  G06F12/1009 ,  G06F2212/7201

Abstract: Devices and techniques are disclosed herein for more efficiently exchanging large amounts of data between a host and a storage system. In an example, a read command can optionally include a read-type indicator. The read-type indicator can allow for exchange of a large amount of data between the host and the storage system using a single read command.

公开(公告)号：US20240160566A1

公开(公告)日：2024-05-16

申请号：US18383746

申请日：2023-10-25

Applicant: Micron Technology, Inc.

Inventor： Marco Redaelli

IPC: G06F12/02 ,  G06F11/07

CPC classification number: G06F12/0292 ,  G06F11/0772 ,  G06F12/0246 ,  G06F2212/7201

Abstract: A memory sub-system with multiple flash translation layer (FTL) tables is disclosed. A host system can utilize a memory sub-system that includes one or more memory components. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system. The FTL provides several services, including translating logical addresses used by the host to physical addresses used to access physical memory. If one FTL table is corrupted, the logical-to-physical mapping of another FTL table may be used, allowing the device to continue to provide read-write access to at least a portion of the memory sub-system. Thus, by use of a secondary FTL table, the reliability of the memory sub-system is improved.

公开(公告)号：US20240152451A1

公开(公告)日：2024-05-09

申请号：US18178887

申请日：2023-03-06

Applicant: SK hynix Inc.

Inventor： Ku Ik KWON ,  Jun Han LEE ,  Byoung Min JIN ,  Gyu Yeul HONG

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/0292 ,  G06F2212/7201

Abstract: A storage device may generate mapping information between a plurality of memory regions and one or more namespaces. The storage device may record information on empty memory regions among the plurality of memory regions in an empty table, and may determine empty memory regions to be mapped to a target namespace among the empty memory regions recorded in the empty table.

公开(公告)号：US11977767B2

公开(公告)日：2024-05-07

申请号：US17693431

申请日：2022-03-14

Applicant: Silicon Motion, Inc.

Inventor： Yi-Kai Pai

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0238 ,  G06F2212/7201

Abstract: A method of caching mapping table for use in a flash memory device having a flash memory controller and a flash memory is provided. The method includes: in response to a host read command, determining whether a group of a logical-to-physical (L2P) required by handling the host read command has been loaded to a DRAM of the flash memory controller; if the required group of the L2P mapping table has not been loaded to the DRAM, loading the required group of the L2P mapping table from the flash memory to a SRAM of the flash memory controller; directly accessing the SRAM to obtain an L2P address associated with the host read command from the required group of the L2P mapping table; and performing a read operation on the flash memory in response to the host read command according to the obtained L2P address.

公开(公告)号：US11971816B2

公开(公告)日：2024-04-30

申请号：US17838832

申请日：2022-06-13

Applicant: Micron Technology, Inc.

Inventor： Binbin Huo

IPC: G06F12/02 ,  G06F12/0817 ,  G06F12/0873 ,  G06F12/0882

CPC classification number: G06F12/0246 ,  G06F12/0253 ,  G06F12/0822 ,  G06F12/0873 ,  G06F12/0882 ,  G06F2212/7201

Abstract: Various embodiments enable sending a notification to a host system based on an address mapping entry miss (or mismatch) on a memory sub-system, which can facilitate an update of one or more address mapping entries stored on the host system.

公开(公告)号：US11960395B2

公开(公告)日：2024-04-16

申请号：US17870414

申请日：2022-07-21

Applicant: Western Digital Technologies, Inc.

Inventor： Amir Shaharabany ,  Shay Vaza

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0608 ,  G06F3/0656 ,  G06F3/0673 ,  G06F12/0292 ,  G06F2212/401 ,  G06F2212/7201

Abstract: The present disclosure generally relates to more efficient use of a delta buffer. To utilize the delta buffer, an efficiency can be gained by utilizing absolute delta entries and relative delta entries. The absolute delta entry will include the type of delta entry, the L2P table index, the L2P table offset, and the PBA. The relative delta entry will include the type of delta entry, the L2P table offset, and the PBA offset. The relative delta entry will utilize about half of the storage space of the absolute delta entry. The relative delta entry can be used after an absolute delta entry so long as the relative delta entry is for data stored in the same block as the previous delta entry. If data is stored in a different block, then the delta entry will be an absolute delta entry.

公开(公告)号：US11960394B2

公开(公告)日：2024-04-16

申请号：US17870407

申请日：2022-07-21

Applicant: Western Digital Technologies, Inc.

Inventor： Amir Shaharabany ,  Shay Vaza

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0608 ,  G06F3/0656 ,  G06F3/0673 ,  G06F12/0292 ,  G06F2212/401 ,  G06F2212/7201

Abstract: The present disclosure generally relates to more efficient use of a delta buffer. To Utilize the delta buffer, an efficiency can be gained by utilizing absolute delta entries and relative delta entries. The absolute delta entry will include the type of delta entry, the L2P table index, the L2P table offset, and the PBA. The relative delta entry will include the type of delta entry, the L2P table offset, and the PBA offset. The relative delta entry will utilize about half of the storage space of the absolute delta entry. The relative delta entry can be used after an absolute delta entry so long as the relative delta entry is for data stored in the same block as the previous delta entry. If data is stored in a different block, then the delta entry will be an absolute delta entry.

公开(公告)号：US11954021B2

公开(公告)日：2024-04-09

申请号：US18075698

申请日：2022-12-06

Applicant: SK hynix Inc.

Inventor： Sung Jin Park ,  Jee Yul Kim

IPC: G06F12/02 ,  G06F3/06 ,  G06F12/0891

CPC classification number: G06F12/0246 ,  G06F3/0614 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0679 ,  G06F12/0253 ,  G06F12/0891 ,  G06F2212/7201

Abstract: The present disclosure relates to a storage device. The storage device includes a memory device including write-completed blocks storing data and free blocks each containing no data and a memory controller controlling the memory device to perform a garbage collection operation to store valid data stored in a victim block, among the write-completed blocks, in one of the free blocks based on the number of map segments including mapping information between logical addresses and physical addresses of the valid data, and erase counts of the free blocks.

公开(公告)号：US11941289B2

公开(公告)日：2024-03-26

申请号：US17204036

申请日：2021-03-17

Applicant: SK hynix Inc.

Inventor： Jung Ae Kim ,  Jee Yul Kim

IPC: G06F3/06 ,  G06F12/0882

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G06F12/0882 ,  G06F2212/7201

Abstract: A memory system includes a memory device including plural memory groups, each memory group including plural non-volatile memory cells; and a controller configured to transmit a command to the memory device so that the memory device performs a data input/output operation within at least one memory group among the plural memory groups, receive a response for the command and a status data regarding the at least one memory group from the memory device, and determine whether the data input/output operation has succeeded or failed based on the response and the status data.

公开(公告)号：US11940926B2

公开(公告)日：2024-03-26

申请号：US17663255

申请日：2022-05-13

Applicant: Micron Technology, Inc.

Inventor： Stephen Hanna

IPC: G06F12/1009 ,  G06F12/02

CPC classification number: G06F12/1009 ,  G06F12/0246 ,  G06F2212/7201

Abstract: Methods, systems, and devices for creating high density logical to physical mapping are described. A memory system may implement storage of mapping information to store the logical addresses and the corresponding physical addresses. A memory system may receive a command associated with data and a corresponding set of logical addresses, and in some cases the memory device may determine that the logical addresses are sequential. The memory device may generate and store a set of compressed entries in a macro level of the mapping information. When the memory system receives a command associated with an exception to the sequential logical addresses, the memory system may update an entry of the macro level to include a pointer to a set of entries in another level of the mapping information.