公开(公告)号：US20160111393A1

公开(公告)日：2016-04-21

申请号：US14885931

申请日：2015-10-16

Applicant: SpectraSensors, Inc.

Inventor： Alfred Feitisch ,  Gabi Neubauer ,  Mathias Schrempel

IPC: H01L23/00 ,  H01S5/022

CPC classification number: H01L24/83 ,  B23K20/023 ,  B23K20/24 ,  B23K2101/42 ,  H01L33/62 ,  H01L2224/73265 ,  H01L2224/83201 ,  H01L2224/8385 ,  H01L2924/12042 ,  H01S5/02212 ,  H01S5/02256 ,  H01S5/0226 ,  H01S5/02264 ,  H01S5/02476 ,  H01S5/0425

Abstract: A first contact surface of a semiconductor laser chip can be formed to a first target surface roughness and a second contact surface of a carrier mounting can be formed to a second target surface roughness. A first bond preparation layer comprising a first metal can optionally be applied to the formed first contact surface, and a second bond preparation layer comprising a second metal can optionally be applied to the formed second contact surface. The first contact surface can be contacted with the second contact surface, and a solderless securing process can secure the semiconductor laser chip to the carrier mounting. Related systems, methods, articles of manufacture, and the like are also described.

Abstract translation: 可以将半导体激光器芯片的第一接触表面形成为第一目标表面粗糙度，并且可以将载体安装的第二接触表面形成为第二目标表面粗糙度。 包含第一金属的第一粘合制备层可以任选地施加到所形成的第一接触表面，并且包括第二金属的第二接合制备层可任选地施加到形成的第二接触表面。 第一接触表面可以与第二接触表面接触，并且无焊接固定工艺可以将半导体激光器芯片固定到载体安装。 还描述了相关系统，方法，制品等。

公开(公告)号：US20160099233A1

公开(公告)日：2016-04-07

申请号：US14879800

申请日：2015-10-09

Applicant: ZIPTRONIX, INC.

Inventor： Paul M. Enquist ,  Gaius Gillman Fountain

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/683 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/2007 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/49866 ,  H01L24/32 ,  H01L24/83 ,  H01L25/50 ,  H01L2221/68359 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/83053 ,  H01L2224/83201 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.

Abstract translation: 一种将具有第一表面的第一衬底与第一绝缘材料和第一接触结构与具有第二表面的第二衬底与第二绝缘材料和第二接触结构集成的方法。 第一绝缘材料直接接合到第二绝缘材料上。 去除第一衬底的一部分以留下剩余部分。 具有与第一基板的CTE基本相同的热膨胀系数（CTE）的第三基板被结合到剩余部分。 粘合的基底被加热以促进第一和第二接触结构之间的电接触。 在加热之后移除第三衬底以提供具有可靠电接触的接合结构。

公开(公告)号：US20160042976A1

公开(公告)日：2016-02-11

申请号：US14921026

申请日：2015-10-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Isabel DE SOUSA ,  Annique LAVOIE ,  Eric SALVAS ,  Michel TURGEON

IPC: H01L21/48 ,  H01L21/3105 ,  H01L21/52 ,  H01L21/56

CPC classification number: H01L23/3675 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/324 ,  H01L21/481 ,  H01L21/4817 ,  H01L21/4882 ,  H01L21/50 ,  H01L21/52 ,  H01L21/563 ,  H01L21/565 ,  H01L22/10 ,  H01L22/12 ,  H01L22/20 ,  H01L23/04 ,  H01L23/367 ,  H01L23/3737 ,  H01L23/42 ,  H01L23/50 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83048 ,  H01L2224/83191 ,  H01L2224/832 ,  H01L2224/83201 ,  H01L2224/838 ,  H01L2224/83855 ,  H01L2224/83908 ,  H01L2224/83986 ,  H01L2924/06 ,  H01L2924/16251 ,  H01L2924/1659 ,  H01L2924/20102 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly.

公开(公告)号：US09179586B2

公开(公告)日：2015-11-03

申请号：US13702173

申请日：2011-07-05

Applicant: Jean Brun

Inventor： Jean Brun

IPC: H05K3/30 ,  H05K13/04 ,  H01L23/498 ,  H01L23/00 ,  H05K1/18 ,  H01L23/13 ,  H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H05K1/02 ,  H05K1/03

CPC classification number: H05K13/046 ,  H01L23/13 ,  H01L23/4985 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/08238 ,  H01L2224/1134 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32237 ,  H01L2224/32238 ,  H01L2224/73204 ,  H01L2224/80006 ,  H01L2224/80007 ,  H01L2224/80201 ,  H01L2224/80903 ,  H01L2224/81005 ,  H01L2224/81007 ,  H01L2224/81191 ,  H01L2224/81201 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/81903 ,  H01L2224/83005 ,  H01L2224/83007 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2224/83385 ,  H01L2224/8385 ,  H01L2224/90 ,  H01L2224/9211 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/0665 ,  H01L2924/12041 ,  H01L2924/12042 ,  H05K1/0281 ,  H05K1/038 ,  H05K1/189 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2203/0108 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A substrate provided with an electrically conducting wire coated with an electrically insulating material is impregnated with a polymerizable material. A reception area for a chip is formed on a surface of the substrate by means of deformation. The housing area is stiffened using the polymerizable material. The chip is disposed in the reception area and an electrical connection area of the chip is connected electrically to the electrically conducting wire of the substrate.

Abstract translation: 设置有涂覆有电绝缘材料的导电线的基板用可聚合材料浸渍。 通过变形在基板的表面上形成用于芯片的接收区域。 使用可聚合材料使住房区域变硬。 芯片设置在接收区域中，并且芯片的电连接区域电连接到基板的导电线。

公开(公告)号：US20150243591A1

公开(公告)日：2015-08-27

申请号：US14190952

申请日：2014-02-26

Applicant: Infineon Technologies AG

Inventor： Carsten von Koblinski ,  Ulrike Fastner ,  Andre Brockmeier ,  Peter Zorn

IPC: H01L23/495 ,  H01L21/52 ,  H01L21/78

CPC classification number: H01L21/52 ,  H01L21/4803 ,  H01L21/683 ,  H01L21/78 ,  H01L23/051 ,  H01L23/3677 ,  H01L23/492 ,  H01L23/49861 ,  H01L24/19 ,  H01L24/20 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0346 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/221 ,  H01L2224/2732 ,  H01L2224/29011 ,  H01L2224/29188 ,  H01L2224/2919 ,  H01L2224/32105 ,  H01L2224/32111 ,  H01L2224/32155 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/82105 ,  H01L2224/82947 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2224/9202 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/13055 ,  H01L2924/15156 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2224/19 ,  H01L2224/83

Abstract: A carrier substrate having a plurality of receptacles each for receiving and carrying a semiconductor chip is provided. Semiconductor chips are arranged in the receptacles, and metal is plated in the receptacles to form a metal structure on and in contact with the semiconductor chips. The carrier substrate is cut to form separate semiconductor devices.

Abstract translation: 提供了具有多个用于接收和携带半导体芯片的插座的载体基板。 半导体芯片布置在插座中，金属电镀在插座中以在半导体芯片上形成金属结构并与其接触。 将载体衬底切割以形成分离的半导体器件。

公开(公告)号：US20150179603A1

公开(公告)日：2015-06-25

申请号：US14411741

申请日：2013-06-05

Applicant: Soitec

Inventor： Ionut Radu ,  Marcel Broekaart ,  Arnaud Castex ,  Gweltaz Gaudin ,  Gregory Riou

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/306

CPC classification number: H01L24/83 ,  H01L21/187 ,  H01L21/30604 ,  H01L21/30625 ,  H01L22/12 ,  H01L23/562 ,  H01L24/32 ,  H01L2224/29124 ,  H01L2224/29155 ,  H01L2224/2916 ,  H01L2224/29169 ,  H01L2224/29171 ,  H01L2224/29176 ,  H01L2224/2918 ,  H01L2224/29181 ,  H01L2224/29184 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83895 ,  H01L2924/01014 ,  H01L2924/0504 ,  H01L2924/10253 ,  H01L2924/201 ,  Y10T428/12493 ,  Y10T428/12639 ,  Y10T428/12646 ,  Y10T428/12653 ,  Y10T428/12674

Abstract: Method for producing a composite structure comprising the direct bonding of at least one first wafer with a second wafer, and comprising a step of initiating the propagation of a bonding wave, where the bonding interface between the first and second wafers after the propagation of the bonding wave has a bonding energy of less than or equal to 0.7 J/m2. The step of initiating the propagation of the bonding wave is performed under one or more of the following conditions: placement of the wafers in an environment at a pressure of less than 20 mbar and/or application to one of the two wafers of a mechanical pressure of between 0.1 MPa and 33.3 MPa. The method further comprises, after the step of initiating the propagation of a bonding wave, a step of determining the level of stress induced during bonding of the two wafers, the level of stress being determined on the basis of a stress parameter Ct calculated using the formula Ct=Rc/Ep, where: Rc corresponds to the radius of curvature (in km) of the two-wafer assembly and Ep corresponds to the thickness (in μm) of the two-wafer assembly. The method further comprises a step of validating the bonding when the level of stress Ct determined is greater than or equal to 0.07.

Abstract translation: 一种制造复合结构的方法，包括至少一个第一晶片与第二晶片的直接结合，并且包括启动键合波的传播的步骤，其中在所述第一和第二晶片传播之后的所述第一和第二晶片之间的结合界面 波具有小于或等于0.7J / m 2的结合能。 启动粘合波传播的步骤是在以下一个或多个条件下进行的：将晶片放置在小于20毫巴的压力的环境中和/或施加到两个晶片之一的机械压力 在0.1MPa和33.3MPa之间。 该方法还包括在开始粘合波的传播的步骤之后，确定在两个晶片的接合期间引起的应力水平的步骤，根据使用第二晶片计算出的应力参数Ct来确定应力水平 公式Ct = Rc / Ep，其中：Rc对应于两晶片组件的曲率半径（km），Ep对应于两晶片组件的厚度（μm）。 该方法还包括当确定的应力Ct大于或等于0.07时验证接合的步骤。

公开(公告)号：US20150076216A1

公开(公告)日：2015-03-19

申请号：US14468660

申请日：2014-08-26

Applicant: Raytheon Company

Inventor： Buu Q. Diep ,  Thomas A. Kocian ,  Roland W. Gooch

IPC: B23K1/20

CPC classification number: B23K1/206 ,  B23K1/0016 ,  B23K1/008 ,  B23K1/20 ,  B23K1/203 ,  B23K3/047 ,  B23K3/08 ,  B23K2101/40 ,  H01L21/67092 ,  H01L21/67173 ,  H01L21/67207 ,  H01L24/27 ,  H01L24/29 ,  H01L24/742 ,  H01L24/75 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/0401 ,  H01L2224/056 ,  H01L2224/27318 ,  H01L2224/27334 ,  H01L2224/2745 ,  H01L2224/2746 ,  H01L2224/2781 ,  H01L2224/27826 ,  H01L2224/291 ,  H01L2224/29144 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/7501 ,  H01L2224/75102 ,  H01L2224/83013 ,  H01L2224/83201 ,  H01L2224/834 ,  H01L2224/83815 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2924/0105 ,  H01L2924/00

Abstract: In certain embodiments, a system includes a deposition system and a plasma/bonding system. The deposition system deposits a solder outwardly from a substrate of a number of substrates. The plasma/bonding system comprises a plasma system configured to plasma clean the substrate and a bonding system configured to bond the substrates. The plasma/bonding system at least reduces reoxidation of the solder. In certain embodiments, a method comprises depositing solder outwardly from a substrate, removing metal oxide from the substrate, and depositing a capping layer outwardly from the substrate to at least reduce reoxidation of the solder.

Abstract translation: 在某些实施例中，系统包括沉积系统和等离子/粘合系统。 沉积系统从许多基底的衬底向外沉积焊料。 等离子体/粘合系统包括构造成等离子体清洁基板的等离子体系统和被配置为结合基板的接合系统。 等离子体/粘合系统至少减少了焊料的再氧化。 在某些实施例中，一种方法包括从衬底向外沉积焊料，从衬底去除金属氧化物，以及从衬底向外沉积覆盖层以至少减少焊料的再氧化。

公开(公告)号：US08970010B2

公开(公告)日：2015-03-03

申请号：US13834196

申请日：2013-03-15

Applicant: Cree, Inc.

Inventor： Fabian Radulescu ,  Helmut Hagleitner ,  Terry Alcorn ,  William T. Pulz

IPC: H01L29/40 ,  H01L23/48 ,  H01L23/52 ,  H01L23/532 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L21/76897 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/76841 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/488 ,  H01L23/53247 ,  H01L23/53252 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/0361 ,  H01L2224/04026 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/05644 ,  H01L2224/26145 ,  H01L2224/2746 ,  H01L2224/2747 ,  H01L2224/2761 ,  H01L2224/29011 ,  H01L2224/2908 ,  H01L2224/29083 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/32238 ,  H01L2224/83191 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/83815 ,  H01L2224/83897 ,  H01L2224/94 ,  H01L2924/01322 ,  H01L2924/12032 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/0105 ,  H01L2224/27013 ,  H01L2924/00012 ,  H01L2224/27 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01022 ,  H01L2924/00

Abstract: Embodiments of a semiconductor wafer having wafer-level die attach metallization on a back-side of the semiconductor wafer, resulting semiconductor dies, and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor wafer includes a semiconductor structure and a front-side metallization that includes front-side metallization elements for a number of semiconductor die areas. The semiconductor wafer also includes vias that extend from a back-side of the semiconductor structure to the front-side metallization elements. A back-side metallization is on the back-side of the semiconductor structure and within the vias. For each via, one or more barrier layers are on a portion of the back-side metallization that is within the via and around a periphery of the via. The semiconductor wafer further includes wafer-level die attach metallization on the back-side metallization other than the portions of the back-side metallization that are within the vias and around the peripheries of the vias.

Abstract translation: 公开了具有晶片级芯片的半导体晶片的实施例，其在半导体晶片的背面上附着金属化，得到的半导体晶粒及其制造方法。 在一个实施例中，半导体晶片包括半导体结构和前侧金属化，其包括用于多个半导体管芯区域的前侧金属化元件。 半导体晶片还包括从半导体结构的背面延伸到前侧金属化元件的通孔。 背面金属化在半导体结构的背面和通孔内。 对于每个通孔，一个或多个阻挡层位于背面金属化的位于通孔内部以及通孔周围的一部分上。 半导体晶片还包括在背面金属化之外的晶片级芯片附接金属化，而不是在通孔内部和周围的通孔周围的后侧金属化部分。

公开(公告)号：US20150048523A1

公开(公告)日：2015-02-19

申请号：US14397038

申请日：2013-04-24

Applicant: Tadatomo SUGA ,  BONDTECH CO., LTD.

Inventor： Tadatomo Suga ,  Akira Yamauchi

IPC: H01L25/065 ,  B23K31/02 ,  H01L21/66 ,  H01L23/00 ,  H01L25/00 ,  H01L25/10 ,  B23K37/04 ,  B23K37/00

CPC classification number: H01L25/0652 ,  B23K31/02 ,  B23K37/00 ,  B23K37/0408 ,  B23K2101/40 ,  H01L21/6836 ,  H01L22/10 ,  H01L23/10 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/09 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/74 ,  H01L24/742 ,  H01L24/743 ,  H01L24/75 ,  H01L24/80 ,  H01L24/81 ,  H01L24/83 ,  H01L24/94 ,  H01L24/95 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0384 ,  H01L2224/03845 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06134 ,  H01L2224/0615 ,  H01L2224/06177 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/09181 ,  H01L2224/1184 ,  H01L2224/11845 ,  H01L2224/13009 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14134 ,  H01L2224/1415 ,  H01L2224/14177 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/27009 ,  H01L2224/2755 ,  H01L2224/27823 ,  H01L2224/2784 ,  H01L2224/27845 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73103 ,  H01L2224/74 ,  H01L2224/7501 ,  H01L2224/75101 ,  H01L2224/75102 ,  H01L2224/7525 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/75283 ,  H01L2224/753 ,  H01L2224/75301 ,  H01L2224/7531 ,  H01L2224/75501 ,  H01L2224/75502 ,  H01L2224/7565 ,  H01L2224/75701 ,  H01L2224/75702 ,  H01L2224/75753 ,  H01L2224/75802 ,  H01L2224/75804 ,  H01L2224/75824 ,  H01L2224/75842 ,  H01L2224/7598 ,  H01L2224/80003 ,  H01L2224/8001 ,  H01L2224/80013 ,  H01L2224/80065 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80143 ,  H01L2224/80201 ,  H01L2224/80203 ,  H01L2224/8022 ,  H01L2224/8023 ,  H01L2224/80447 ,  H01L2224/8083 ,  H01L2224/80907 ,  H01L2224/81002 ,  H01L2224/8101 ,  H01L2224/81013 ,  H01L2224/81065 ,  H01L2224/8113 ,  H01L2224/81132 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81203 ,  H01L2224/8122 ,  H01L2224/8123 ,  H01L2224/81447 ,  H01L2224/81801 ,  H01L2224/81805 ,  H01L2224/8183 ,  H01L2224/81907 ,  H01L2224/83002 ,  H01L2224/8301 ,  H01L2224/83013 ,  H01L2224/83048 ,  H01L2224/83051 ,  H01L2224/83065 ,  H01L2224/83091 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/83136 ,  H01L2224/83143 ,  H01L2224/83193 ,  H01L2224/83201 ,  H01L2224/83203 ,  H01L2224/8322 ,  H01L2224/8323 ,  H01L2224/83234 ,  H01L2224/83355 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/8383 ,  H01L2224/83894 ,  H01L2224/83907 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/10157 ,  H01L2924/10253 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/80 ,  H01L2224/83 ,  H01L2924/00

Abstract: [Problem] Provided is a technique for bonding chips efficiently onto a wafer to establish an electrical connection and raise mechanical strength between the chips and the wafer or between the chips that are chips laminated onto each other in the state that resin and other undesired residues do not remain on a bond interface therebetween.[Solution] A method for bonding plural chips each having a chip-side-bond-surface having metal regions to a substrate having plural bond portions has the step (S1) of subjecting the metal regions of the chip-side-bond-surface to surface activating treatment and hydrophilizing treatment; the step (S2) of subjecting the bond portions of the substrate to surface activating treatment and hydrophilizing treatment; the step (S3) of fitting the chips subjected to the surface activating treatment and the hydrophilizing treatment onto the corresponding bond portions of the substrate subjected to the surface activating treatment and the hydrophilizing treatment to bring the metal regions of the chips into contact with the bond portions of the substrate; and the step (S4) of heating the resultant structure, which includes the substrate, and the chips fitted onto the substrate.

Abstract translation: [问题]提供了一种将芯片有效地接合到晶片上以建立电连接并提高芯片和晶片之间或芯片之间的机械强度的技术，该芯片是在树脂和其它不期望的残留物的状态下彼此层压的芯片 不保留在它们之间的结合界面上。 [解决方案]将具有金属区域的具有芯片侧接合面的多个芯片接合到具有多个结合部的基板的方法具有将芯片侧接合面的金属区域 表面活化处理和亲水处理; 对所述基板的所述接合部进行表面活化处理和亲水化处理的工序（S2） 将经过表面活化处理和亲水化处理的芯片装配到经过表面活化处理的基板的相应接合部分和亲水化处理上以使芯片的金属区域与键接触的步骤（S3） 基板的一部分; 以及加热包括基板的所得结构和安装在基板上的芯片的步骤（S4）。

公开(公告)号：US08957521B2

公开(公告)日：2015-02-17

申请号：US14114337

申请日：2012-12-26

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Taichi Nakamura ,  Hidetoshi Kitaura

IPC: H01L23/12 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  B23K35/02 ,  B23K35/22 ,  H01L23/488 ,  H01L23/492 ,  B23K35/26 ,  B23K35/30 ,  H01L23/495

CPC classification number: H01L24/05 ,  B23K35/0261 ,  B23K35/0272 ,  B23K35/22 ,  B23K35/264 ,  B23K35/302 ,  H01L23/488 ,  H01L23/492 ,  H01L23/49513 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/2712 ,  H01L2224/27334 ,  H01L2224/29083 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/32507 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83065 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2224/83411 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8381 ,  H01L2224/83986 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/12042 ,  H01L2924/203 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/01083 ,  H01L2224/8321 ,  H01L2924/0002

Abstract: A mounted structure includes an electrode of a substrate, an electrode of a semiconductor element, and a mounted layers for bonding the electrode of the substrate and the electrode of the semiconductor element, and the mounted layers includes: a first intermetallic compound layer containing a CuSn-based intermetallic compound; a Bi layer; a second intermetallic compound layer containing a CuSn-based intermetallic compound; a Cu layer; and a third intermetallic compound layer containing a CuSn-based intermetallic compound, and the above layers are sequentially arranged from the electrode of the substrate toward the electrode of the semiconductor element to configure the mounted layers.

Abstract translation: 安装结构包括基板的电极，半导体元件的电极和用于接合基板的电极和半导体元件的电极的安装层，并且安装的层包括：含有CuSn的第一金属间化合物层 基金属间化合物; 铋层; 包含CuSn基金属间化合物的第二金属间化合物层; 铜层; 以及含有CuSn基金属间化合物的第三金属间化合物层，并且从基板的电极向半导体元件的电极依次配置上述层，以配置安装层。