公开(公告)号：US20170005668A1

公开(公告)日：2017-01-05

申请号：US15137233

申请日：2016-04-25

Applicant: Renesas Electronics Corporation

Inventor： Hiroki TAKADA ,  Atsushi TANGODA

IPC: H03M1/46

CPC classification number: H03M1/46 ,  H03M1/08 ,  H03M1/12 ,  H03M1/468

Abstract: A successive approximation ADC capable of reducing deterioration in AD conversion accuracy due to noise is provided. An AD converter according to an embodiment includes: a DA converter that generates a comparison voltage based on a sampling value obtained by sampling an analog signal, and a successive approximation control signal; a reference voltage generation circuit that generates a reference voltage used for the successive approximation process; a comparator that compares the comparison voltage with the reference voltage and outputs a successive approximation result; a successive approximation processing unit that generates the successive approximation control signal based on the successive approximation result; and a storage unit that stores an expected value of the AD conversion process. The reference voltage generation circuit generates the reference voltage based on the expected value stored in the storage unit.

Abstract translation: 提供了能够降低由于噪声导致的AD转换精度恶化的逐次逼近ADC。 根据实施例的AD转换器包括：DA转换器，其基于通过对模拟信号进行采样获得的采样值和逐次逼近控制信号来产生比较电压; 产生用于逐次逼近处理的参考电压的参考电压产生电路; 将比较电压与参考电压进行比较并输出逐次逼近结果的比较器; 逐次逼近处理单元，其基于所述逐次近似结果生成所述逐次逼近控制信号; 以及存储单元，其存储AD转换处理的期望值。 参考电压产生电路基于存储在存储单元中的期望值产生参考电压。

公开(公告)号：US20170003810A1

公开(公告)日：2017-01-05

申请号：US15199010

申请日：2016-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： San-Ho BYUN ,  Chadong KIM ,  Jinchul LEE ,  Bumsoo KIM ,  Junchul PARK ,  Kyeonggon LEE

IPC: G06F3/041 ,  H03M3/00 ,  H03M1/08 ,  G06F3/044

CPC classification number: H03M1/08 ,  G06F3/044 ,  H03M1/144 ,  H03M1/145 ,  H03M3/458 ,  H03M3/464

Abstract: A touch processor circuit includes a capacitance-to-voltage converter and an analog-to-digital converter. The capacitance-to-voltage converter converts an input signal transmitted from a touch sensor into a conversion signal corresponding to a capacitance of the touch sensor. The analog-to-digital converter digitizes the conversion signal transmitted from the capacitance-to-voltage converter and generates a digital value. The analog-to-digital converter includes a first converter, a second converter, and a combination logic circuit. The first converter calculates upper bits of the digital value based on the conversion signal during a first time period. The second converter calculates lower bits of the digital value based on a residue component signal transmitted from the first converter during a second time period. The combination logic circuit combines the upper bits and the lower bits and generates the digital value.

Abstract translation: 触摸处理器电路包括电容 - 电压转换器和模 - 数转换器。 电容 - 电压转换器将从触摸传感器发送的输入信号转换成对应于触摸传感器的电容的转换信号。 模数转换器对从电容 - 电压转换器传输的转换信号进行数字化，并产生一个数字值。 模数转换器包括第一转换器，第二转换器和组合逻辑电路。 第一转换器基于第一时间段内的转换信号来计算数字值的高位。 第二转换器基于在第二时间段期间从第一转换器发送的残留分量信号来计算数字值的较低位。 组合逻辑电路组合高位和低位并产生数字值。

公开(公告)号：US09484970B2

公开(公告)日：2016-11-01

申请号：US14988809

申请日：2016-01-06

Applicant: SPATIAL DIGITAL SYSTEMS, INC.

Inventor： Donald C. D. Chang ,  Tzer-Hso Lin ,  Yuanchang Liu

IPC: H03M1/12 ,  H04B1/12 ,  H03M1/06 ,  H04B1/04 ,  H04B7/10 ,  H03M1/00 ,  H03M1/08 ,  H03M1/18 ,  H03M1/20 ,  H04L27/06

CPC classification number: H03M1/002 ,  H03M1/0641 ,  H03M1/08 ,  H03M1/12 ,  H03M1/1205 ,  H03M1/1215 ,  H03M1/188 ,  H03M1/20 ,  H04B1/0475 ,  H04B1/123 ,  H04B7/10 ,  H04L27/06

Abstract: A novel noise injection technique is presented to improve dynamic range with low resolution and low speed analog to digital converters. This technique combines incoming signal and noise signal with wave front de-multiplexer and split into several channels. Then low resolution and low speed analog to digital converters are used to sample each channels. All signals are recovered using wave front multiplexer. For advanced design, ground diagnostic signals with optimizing processor can be added to guarantee recovery quality.

公开(公告)号：US20160305999A1

公开(公告)日：2016-10-20

申请号：US14688336

申请日：2015-04-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chao Chieh LI ,  Ruey-Bin SHEEN

IPC: G01R29/26 ,  H03M1/10 ,  H03L7/085

CPC classification number: G01R29/26 ,  H03M1/08 ,  H03M1/109

Abstract: A flicker noise measurement circuit includes a first section. The first section includes a plurality of first stages connected in series. The first section includes a first feedback switching element configured to selectively feedback an output of the plurality of first stages to an input of the plurality of first stages. The first section includes a first section connection switching element. The flicker noise measurement circuit includes a second section connected to the first section. The second section includes a plurality of second stages connected in series, wherein the first section connection switching element is configured to selectively connect the plurality of second stages to the plurality of first stages. The second section includes a second feedback switching element configured to selectively feedback an output of the plurality of second stages to the input of the plurality of first stages.

Abstract translation: 闪烁噪声测量电路包括第一部分。 第一部分包括串联连接的多个第一级。 第一部分包括第一反馈开关元件，其被配置为选择性地将多个第一级的输出反馈到多个第一级的输入。 第一部分包括第一部分连接开关元件。 闪烁噪声测量电路包括连接到第一部分的第二部分。 第二部分包括串联连接的多个第二级，其中第一部分连接开关元件构造成选择性地将多个第二级连接到多个第一级。 第二部分包括第二反馈开关元件，其被配置为选择性地将多个第二级的输出反馈到多个第一级的输入。

公开(公告)号：US20160294407A1

公开(公告)日：2016-10-06

申请号：US15081162

申请日：2016-03-25

Applicant: LAPIS SEMICONDUCTOR CO., LTD.

Inventor： HIROYUKI KIKUTA

IPC: H03M1/78

CPC classification number: H03M1/785 ,  H03M1/08

Abstract: The present disclosure provides an R-2R ladder resistor circuit including: plural first resistance elements, one end of each being connected to an input terminal; plural second resistance elements, one end of each being connected to a reference potential; plural third resistance elements, one end of each being connected to an output terminal; and plural switching connection sections that are each in correspondence relationships with th first resistance elements, the second resistance elements, and the third resistance elements, and that connect the input terminal and the output terminal according to a bit signal, wherein, according to the bit signal, each switching connection section switchably connects another end of the third resistance element to another end of the first resistance element or to another end of the second resistance element, among the first resistance element, the second resistance element, and the third resistance element corresponding thereto.

Abstract translation: 本公开提供了一种R-2R梯形电阻电路，包括：多个第一电阻元件，其一端连接到输入端; 多个第二电阻元件，其一端连接到参考电位; 多个第三电阻元件，其一端连接到输出端子; 以及多个与第一电阻元件，第二电阻元件和第三电阻元件对应关系的开关连接部，并且根据位信号连接输入端子和输出端子，其中，根据该位 信号，每个开关连接部分将所述第三电阻元件的另一端与所述第一电阻元件的另一端或所述第二电阻元件的另一端可切换地连接，所述第一电阻元件，所述第二电阻元件和所述第三电阻元件对应 到此。

公开(公告)号：US20160261276A1

公开(公告)日：2016-09-08

申请号：US14994564

申请日：2016-01-13

Applicant: DENSO CORPORATION

Inventor： Shogo KAWAHARA ,  Tomohiro NEZUKA

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03M1/08 ,  H03M1/765

Abstract: A D/A converter is configured to output tri-level potentials from an output terminal. A high potential terminal and the output terminal are connected through a p-type MOS transistor. An intermediate potential terminal and the output terminal are connected through p-type and n-type MOS transistors, which are connected in series and have low threshold voltages. A low potential terminal and the output terminal are connected through an n-type MOS transistor. The p-type MOS transistor and the n-type MOS transistor connected to the intermediate potential terminal have a positive voltage and a negative voltage between gate-source paths in off-states, respectively, and a substrate bias effect and hence remain in the off-state stably.

Abstract translation: D / A转换器被配置为从输出端子输出三电平电位。 高电位端子和输出端子通过p型MOS晶体管连接。 中间电位端子和输出端子通过串联连接并具有低阈值电压的p型和n型MOS晶体管连接。 低电位端子和输出端子通过n型MOS晶体管连接。 连接到中间电位端子的p型MOS晶体管和n型MOS晶体管分别在截止状态下的栅极 - 源极之间具有正电压和负电压以及衬底偏置效应，因此保持在截止状态 状态稳定。

公开(公告)号：US20160227145A1

公开(公告)日：2016-08-04

申请号：US15078984

申请日：2016-03-23

Applicant: Sony Corporation

Inventor： Toshiaki Nagai ,  Ken Koseki ,  Yosuke Ueno ,  Atsushi Suzuki

IPC: H04N5/378 ,  H01L27/146 ,  H04N5/225

CPC classification number: H04N5/363 ,  H01L27/14612 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14643 ,  H01L2924/0002 ,  H03M1/08 ,  H03M1/0863 ,  H03M1/123 ,  H03M1/56 ,  H04N5/2253 ,  H04N5/359 ,  H04N5/374 ,  H04N5/37457 ,  H04N5/378 ,  H01L2924/00

Abstract: A semiconductor apparatus, a solid-state image sensing apparatus, and a camera system capable of reducing interference between signals transmitted through adjacent via holes, preventing an increase in the number of the via holes, reducing the area of a chip having sensors thereon and the number of mounting steps thereof. First and second chips are bonded together to form a laminated structure, a wiring between the first chip and the second chip being connected through via holes, the first chip transmitting signals obtained by time-discretizing analog signals generated by respective sensors to the second chip through the corresponding via holes, the second chip sampling the signals transmitted from the first chip through the via holes at a timing different from a timing at which the signals are sampled by the first chip and quantizing the sampled signals to obtain digital signals.

Abstract translation: 一种半导体装置，固态图像感测装置和能够减少通过相邻通孔传播的信号之间的干扰的照相机系统，防止了通孔数量的增加，减少了具有传感器的芯片的面积和 其安装步骤的数量。 第一芯片和第二芯片被结合在一起以形成层叠结构，第一芯片和第二芯片之间的布线通过通孔连接，第一芯片通过时间离散由各个传感器产生的模拟信号获得的信号到第二芯片 对应的通孔，第二芯片在与第一芯片对信号进行采样的定时不同的定时对通过通孔的第一芯片发送的信号进行采样，并量化采样信号以获得数字信号。

公开(公告)号：US09350929B2

公开(公告)日：2016-05-24

申请号：US14348722

申请日：2012-10-10

Applicant: Sony Corporation

Inventor： Toshiaki Nagai ,  Ken Koseki ,  Yosuke Ueno ,  Atsushi Suzuki

IPC: H04N5/374 ,  H04N5/378 ,  H03M1/08 ,  H04N5/359 ,  H03M1/56 ,  H03M1/12 ,  H01L27/146

CPC classification number: H04N5/363 ,  H01L27/14612 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14643 ,  H01L2924/0002 ,  H03M1/08 ,  H03M1/0863 ,  H03M1/123 ,  H03M1/56 ,  H04N5/2253 ,  H04N5/359 ,  H04N5/374 ,  H04N5/37457 ,  H04N5/378 ,  H01L2924/00

Abstract: A semiconductor apparatus, a solid-state image sensing apparatus, and a camera system capable of reducing interference between signals transmitted through adjacent via holes, preventing an increase in the number of the via holes, reducing the area of a chip having sensors thereon and the number of mounting steps thereof. A first chip and a second chip are bonded together to form a laminated structure, a wiring between the first chip and the second chip being connected through via holes, the first chip transmitting signals obtained by time-discretizing analog signals generated by respective sensors to the second chip through the corresponding via holes, the second chip having a function of sampling the signals transmitted from the first chip through the via holes at a timing different from a timing at which the signals are sampled by the first chip and a function of quantizing the sampled signals to obtain digital signals.

Abstract translation: 一种半导体装置，固态图像感测装置和能够减少通过相邻通孔传播的信号之间的干扰的照相机系统，防止了通孔数量的增加，减少了具有传感器的芯片的面积和 其安装步骤的数量。 第一芯片和第二芯片被结合在一起以形成层叠结构，第一芯片和第二芯片之间的布线通过通孔连接，第一芯片通过时间离散由各个传感器产生的模拟信号获得的信号到 第二芯片通过对应的通孔，第二芯片具有在与第一芯片对信号采样的定时不同的定时通过通孔对从第一芯片发送的信号进行采样的功能，以及量化 采样信号以获得数字信号。

公开(公告)号：US09232165B2

公开(公告)日：2016-01-05

申请号：US13585029

申请日：2012-08-14

Applicant: Kazuhiro Saito ,  Hiroki Hiyama ,  Tetsuya Itano ,  Kohichi Nakamura

Inventor： Kazuhiro Saito ,  Hiroki Hiyama ,  Tetsuya Itano ,  Kohichi Nakamura

IPC: H01L27/146 ,  H04N5/378 ,  H04N5/357 ,  H03M1/08

CPC classification number: H04N5/378 ,  H03M1/08 ,  H03M1/123 ,  H03M1/56 ,  H04N5/357 ,  H04N5/3575

Abstract: A solid-state imaging apparatus includes: a ramp signal generator for generating first and second time-changing ramp signals during first and second analog-to-digital conversion periods, respectively; comparators for comparing a reset signal of a pixel with the first ramp signal during the first analog-to-digital conversion period, and comparing a pixel signal with the second ramp signal during the second analog-to-digital conversion period; and memories for storing, as first and second digital data, count values of counting from a start of changing the first and second ramp signals until an inversion of outputs of the comparators, during the first and second analog-to-digital conversion periods, wherein the ramp signal generator supplies a current from a current generator to a first capacitor element by a sampling and holding operation of a switch, and generates the first and second ramp signals based on the same bias voltage held by the first capacitor element.

Abstract translation: 固态成像装置包括：斜坡信号发生器，分别在第一和第二模数转换周期期间产生第一和第二时变斜坡信号; 比较器，用于在第一模数转换周期期间比较像素的复位信号和第一斜坡信号，以及在第二模数转换周期期间比较像素信号与第二斜坡信号; 以及存储器，用于作为第一和第二数字数据存储从开始改变第一和第二斜坡信号开始的计数值，直到在第一和第二模数转换周期期间比较器的输出反转，其中 斜坡信号发生器通过开关的采样和保持操作将电流从电流发生器提供给第一电容器元件，并且基于由第一电容器元件保持的相同偏置电压产生第一和第二斜坡信号。

公开(公告)号：US20150301109A1

公开(公告)日：2015-10-22

申请号：US14255924

申请日：2014-04-17

Applicant: Colin Patrick O'Flynn

Inventor： Colin Patrick O'Flynn

IPC: G01R31/319 ,  G01R31/28

CPC classification number: G01R31/3191 ,  G01R31/2851 ,  G01R31/31707 ,  G01R31/31726 ,  H03M1/08

Abstract: Methods and apparatus are provided for sampling an indicator of the internal state of an embedded system or integrated circuit, where the indicator is sampled in a manner synchronous to the internal clock of the embedded system or integrated circuit. The resulting samples can be used for determining secret data within the embedded system or integrated circuit, detecting failures, or detecting counterfeit devices.

Abstract translation: 提供了用于对嵌入式系统或集成电路的内部状态的指示符进行采样的方法和装置，其中以与嵌入式系统或集成电路的内部时钟同步的方式对指示符进行采样。 所得到的样本可用于确定嵌入式系统或集成电路中的秘密数据，检测故障或检测假冒设备。