公开(公告)号：US20120315717A1

公开(公告)日：2012-12-13

申请号：US13200379

申请日：2011-09-23

Applicant: Dong-Wook Park ,  Jong-Hyun Park

Inventor： Dong-Wook Park ,  Jong-Hyun Park

IPC: H01L51/56 ,  H05K3/02 ,  H01L21/336

CPC classification number: H01L27/124 ,  H01L27/1259 ,  H01L29/42384 ,  H01L29/78645 ,  H05K3/062 ,  H05K3/064 ,  H05K2201/0361 ,  H05K2203/0554 ,  H05K2203/0597 ,  Y10T29/49156

Abstract: A method of manufacturing a wire may include forming a wire pattern, which at least includes a first conductive layer, a second conductive layer, and a third conductive layer arranged in the order stated on a substrate. At least the second conductive layer may have higher etch selectivity than the first and third conductive layers. Side holes may be formed by removing portions of the second conductive layer at ends of the wire pattern, and fine wires may be formed by injecting a masking material into the side holes and patterning the wire pattern by using the masking material as a mask.

Abstract translation: 线的制造方法可以包括形成至少包括第一导电层，第二导电层和在基板上按顺序排列的第三导电层的布线图案。 至少第二导电层可具有比第一和第三导电层更高的蚀刻选择性。 可以通过在线图案的端部去除第二导电层的部分来形成侧孔，并且可以通过将掩模材料注入侧孔中并且通过使用掩模材料作为掩模来图案化线图案来形成细线。

公开(公告)号：US08049114B2

公开(公告)日：2011-11-01

申请号：US12408719

申请日：2009-03-22

Applicant: Kuo-Ching Chen ,  Tsung-Yuan Chen ,  Cheng-Pin Chien

Inventor： Kuo-Ching Chen ,  Tsung-Yuan Chen ,  Cheng-Pin Chien

IPC: H05K1/03

CPC classification number: H01L23/3128 ,  H01L21/4857 ,  H01L21/56 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/183 ,  H05K1/186 ,  H05K3/06 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4697 ,  H05K2201/0361 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/308 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2224/0401

Abstract: A method of making a package substrate includes providing a cladding sheet comprising a first metal layer, a second metal layer and an intermediate layer between the first and second metal layers; etching away a portion of the first metal layer to expose a portion of the intermediate layer thereby forming a metal island body; laminating a first copper clad on the cladding sheet comprising a first copper foil and a first insulating layer; patterning the first copper foil to form a first circuit trace; patterning the second metal layer to form a second circuit trace; removing the metal island body to form a cavity in the first insulating layer; and removing the intermediate layer from bottom of the cavity.

Abstract translation: 制造封装衬底的方法包括提供包括第一金属层，第二金属层和第一和第二金属层之间的中间层的覆层片; 蚀刻掉第一金属层的一部分以暴露中间层的一部分，从而形成金属岛体; 在包括第一铜箔和第一绝缘层的包层片上层叠第一铜包层; 图案化第一铜箔以形成第一电路迹线; 图案化第二金属层以形成第二电路迹线; 去除所述金属岛体以在所述第一绝缘层中形成空腔; 以及从腔的底部去除中间层。

公开(公告)号：US07964106B2

公开(公告)日：2011-06-21

申请号：US12129689

申请日：2008-05-30

Applicant: Chang-Fu Chen

Inventor： Chang-Fu Chen

IPC: H01B13/00 ,  H01L21/00

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L23/49822 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/81136 ,  H01L2224/81801 ,  H05K3/06 ,  H05K3/20 ,  H05K3/4007 ,  H05K3/4652 ,  H05K3/4682 ,  H05K2201/0361 ,  H05K2201/0367 ,  H05K2203/0353 ,  H05K2203/0384 ,  Y10T29/49155 ,  Y10T29/49169

Abstract: A method of fabricating a packaging substrate is disclosed. A cladding sheet comprised of a first metal foil, a second metal foil and an etch stop layer interposed between the first and second metal foils is provided. The first metal foil is then patterned into a first circuit trace. An insulating layer is laminated onto the first circuit trace. Thereafter, the second metal foil is patterned into a plurality of bump pads. The etch stop layer that is not covered by the bump pads is stripped off. A solder mask is applied to fill the spacing between the bump pads. A top surface of each of the bump pads is etched to form a bonding aperture in a self-aligned fashion.

Abstract translation: 公开了一种制造封装衬底的方法。 提供由第一金属箔，第二金属箔和介于第一和第二金属箔之间的蚀刻停止层构成的覆层片。 然后将第一金属箔图案化成第一电路迹线。 绝缘层被层压到第一电路迹线上。 此后，将第二金属箔图案化成多个凸块焊盘。 剥离不被凸块焊接的蚀刻停止层被剥离。 施加焊接掩模以填充凸块之间的间隔。 每个凸块焊盘的顶表面被蚀刻以自对准的方式形成接合孔。

公开(公告)号：US07911805B2

公开(公告)日：2011-03-22

申请号：US11824484

申请日：2007-06-29

Applicant: Belgacem Haba

Inventor： Belgacem Haba

IPC: H01R12/16

CPC classification number: H05K3/4007 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/181 ,  H05K3/06 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2203/0384 ,  Y10T29/49144 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of forming contacts for an interconnection element, includes (a) joining a conductive element to an interconnection element having multiple wiring layers, (b) patterning the conductive element to form conductive pins, and (c) electrically interconnecting the conductive pins with conductive features of the interconnection element. A multiple wiring layer interconnection element having an exposed pin interface, includes an interconnection element having multiple wiring layers separated by at least one dielectric layer, the wiring layers including a plurality of conductive features exposed at a first face of the interconnection element, a plurality of conductive pins protruding in a direction away from the first face, and metal features electrically interconnecting the conductive features with the conductive pins.

Abstract translation: 一种形成用于互连元件的触点的方法包括：（a）将导电元件连接到具有多个布线层的互连元件，（b）图案化导电元件以形成导电引脚，以及（c）将导电引脚与导电 互连元件的特征。 具有露出的针接口的多重配线层互连元件包括具有由至少一个电介质层隔开的多个布线层的互连元件，所述布线层包括在所述互连元件的第一面上露出的多个导电特征， 导电引脚沿远离第一面的方向突出，并且金属特征将导电特征与导电引脚电连接。

公开(公告)号：US07632708B2

公开(公告)日：2009-12-15

申请号：US11318822

申请日：2005-12-27

Applicant: Belgacem Haba ,  David B. Tuckerman

Inventor： Belgacem Haba ,  David B. Tuckerman

IPC: H01L21/00

CPC classification number: H05K3/4007 ,  H01L2224/16225 ,  H05K3/062 ,  H05K3/4038 ,  H05K3/4647 ,  H05K2201/0361 ,  H05K2201/0367 ,  H05K2203/0384

Abstract: Methods for making a microelectronic component including a plurality of conductive posts extending and projecting away from a flexible substrate, wherein at least some of the conductive posts are electrically connected to a plurality of traces exposed on the flexible substrate.

Abstract translation: 用于制造微电子部件的方法，所述微电子部件包括从柔性基板延伸并远离的多个导电柱，其中至少一些导电柱电连接到暴露在柔性基板上的多个迹线。

公开(公告)号：US07480151B2

公开(公告)日：2009-01-20

申请号：US12000173

申请日：2007-12-10

Applicant: Yoichi Miura

Inventor： Yoichi Miura

IPC: H05K7/00

CPC classification number: H01L24/16 ,  H01L21/4857 ,  H01L2224/11902 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K3/064 ,  H05K3/205 ,  H05K3/243 ,  H05K3/4007 ,  H05K3/423 ,  H05K3/4682 ,  H05K2201/0361 ,  H05K2201/0367 ,  H05K2201/096 ,  H05K2203/0384 ,  H05K2203/0571 ,  H05K2203/0733 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/0401

Abstract: A wiring board according to the present invention includes a wiring part formed of one or more layers, a first terminal area disposed on one side of the wiring part in a projecting manner, and a second terminal area disposed on the other side of the wiring part. A resist having an opening for a first terminal area is formed on a surface of a composite made of a plurality of metal layers. A part of a first metal layer of the composite is etched through the opening for a first terminal area to form a hole. The hole is subjected to an electroless plating through the opening of the resist. Thus, the hole is filled with an electroplated layer to form a first terminal area. Then, the resist is removed from the composite, and a wiring layer is formed thereon. Subsequently, a solder resist having an opening for a second terminal area is disposed on the wiring layer. The opening of a second terminal area of the solder resist is subjected to an electroplating so as to form a second terminal area. Removing remaining parts of the composite, a wiring board is completed.

Abstract translation: 根据本发明的布线板包括由一层或多层形成的布线部分，以布置方式布置在布线部分的一侧上的第一端子区域和布置在布线部分的另一侧上的第二端子区域 。 在由多个金属层制成的复合体的表面上形成具有用于第一端子区域的开口的抗蚀剂。 复合材料的第一金属层的一部分通过开口蚀刻以形成第一端子区域以形成孔。 通过抗蚀剂的开口对该孔进行化学镀。 因此，孔填充有电镀层以形成第一末端区域。 然后，将抗蚀剂从复合材料上除去，并在其上形成布线层。 随后，在布线层上设置具有用于第二端子区的开口的阻焊剂。 对阻焊剂的第二端子区域的开口进行电镀以形成第二端子区域。 拆除复合材料的剩余部分，完成接线板。

公开(公告)号：US20080289868A1

公开(公告)日：2008-11-27

申请号：US12182908

申请日：2008-07-30

Applicant: Hidehiro Nakamura ,  Akishi Nakaso ,  Shigeharu Arike ,  Fumio Inoue ,  Tetsuya Enomoto ,  Norio Moriike ,  Kousuke Hiroki

Inventor： Hidehiro Nakamura ,  Akishi Nakaso ,  Shigeharu Arike ,  Fumio Inoue ,  Tetsuya Enomoto ,  Norio Moriike ,  Kousuke Hiroki

IPC: H05K1/11 ,  H05K1/16

CPC classification number: H05K3/4617 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/0097 ,  H05K3/06 ,  H05K3/244 ,  H05K3/4038 ,  H05K3/4623 ,  H05K3/4632 ,  H05K3/4647 ,  H05K2201/0141 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/0152 ,  H05K2203/0156 ,  H05K2203/0384 ,  H05K2203/0733 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: The present invention provides a connection board that is formed by an insulating resin composition layer made of one layer or two or more layers and a connection conductor that is formed so as to pass through the insulating resin composition layer in its thickness direction at a position where a conductor circuit is connected, and a multi-layer wiring board, a substrate for semiconductor package and a semiconductor package using the connection board, and methods for manufacturing them.

公开(公告)号：US20080106880A1

公开(公告)日：2008-05-08

申请号：US12000173

申请日：2007-12-10

Applicant: Yoichi Miura

Inventor： Yoichi Miura

IPC: H05K7/00

CPC classification number: H01L24/16 ,  H01L21/4857 ,  H01L2224/11902 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/81191 ,  H01L2224/814 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K3/064 ,  H05K3/205 ,  H05K3/243 ,  H05K3/4007 ,  H05K3/423 ,  H05K3/4682 ,  H05K2201/0361 ,  H05K2201/0367 ,  H05K2201/096 ,  H05K2203/0384 ,  H05K2203/0571 ,  H05K2203/0733 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/0401

Abstract: A wiring board according to the present invention includes a wiring part formed of one or more layers, a first terminal area disposed on one side of the wiring part in a projecting manner, and a second terminal area disposed on the other side of the wiring part. A resist having an opening for a first terminal area is formed on a surface of a composite made of a plurality of metal layers. A part of a first metal layer of the composite is etched through the opening for a first terminal area to form a hole. The hole is subjected to an electroless plating through the opening of the resist. Thus, the hole is filled with an electroplated layer to form a first terminal area. Then, the resist is removed from the composite, and a wiring layer is formed thereon. Subsequently, a solder resist having an opening for a second terminal area is disposed on the wiring layer. The opening of a second terminal area of the solder resist is subjected to an electroplating so as to form a second terminal area. Removing remaining parts of the composite, a wiring board is completed.

Abstract translation: 根据本发明的布线板包括由一层或多层形成的布线部分，以布置方式布置在布线部分的一侧上的第一端子区域和布置在布线部分的另一侧上的第二端子区域 。 在由多个金属层制成的复合体的表面上形成具有用于第一端子区域的开口的抗蚀剂。 复合材料的第一金属层的一部分通过开口蚀刻以形成第一端子区域以形成孔。 通过抗蚀剂的开口对该孔进行化学镀。 因此，孔填充有电镀层以形成第一末端区域。 然后，将抗蚀剂从复合材料上除去，并在其上形成布线层。 随后，在布线层上设置具有用于第二端子区的开口的阻焊剂。 对阻焊剂的第二端子区域的开口进行电镀以形成第二端子区域。 拆除复合材料的剩余部分，完成接线板。

公开(公告)号：US20070148941A1

公开(公告)日：2007-06-28

申请号：US11318822

申请日：2005-12-27

Applicant: Belgacem Haba ,  David Tuckerman

Inventor： Belgacem Haba ,  David Tuckerman

IPC: H01L21/44

CPC classification number: H05K3/4007 ,  H01L2224/16225 ,  H05K3/062 ,  H05K3/4038 ,  H05K3/4647 ,  H05K2201/0361 ,  H05K2201/0367 ,  H05K2203/0384

Abstract: Methods for making a microelectronic component including a plurality of conductive posts extending and projecting away from a flexible substrate, wherein at least some of the conductive posts are electrically connected to a plurality of traces exposed on the flexible substrate.

Abstract translation: 用于制造微电子部件的方法，所述微电子部件包括从柔性基板延伸并远离的多个导电柱，其中至少一些导电柱电连接到暴露在柔性基板上的多个迹线。

公开(公告)号：US20060162956A1

公开(公告)日：2006-07-27

申请号：US10500119

申请日：2002-12-24

Applicant: Hidehiro Nakamura ,  Akishi Nakaso ,  Shigeharu Arike ,  Fumio Inoue ,  Tetsduya Enomoto ,  Norio Moriike ,  Kousuke Hiroki

Inventor： Hidehiro Nakamura ,  Akishi Nakaso ,  Shigeharu Arike ,  Fumio Inoue ,  Tetsduya Enomoto ,  Norio Moriike ,  Kousuke Hiroki

IPC: H05K1/03 ,  H05K1/09 ,  H05K1/11

CPC classification number: H05K3/4617 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/0097 ,  H05K3/06 ,  H05K3/244 ,  H05K3/4038 ,  H05K3/4623 ,  H05K3/4632 ,  H05K3/4647 ,  H05K2201/0141 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/0152 ,  H05K2203/0156 ,  H05K2203/0384 ,  H05K2203/0733 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: The present invention provides a connection board that is formed by an insulating resin composition layer made of one layer or two or more layers and a connection conductor that is formed so as to pass through the insulating resin composition layer in its thickness direction at a position where a conductor circuit is connected, and a multi-layer wiring board, a substrate for semiconductor package and a semiconductor package using the connection board, and methods for manufacturing them.

Abstract translation: 本发明提供一种由一层或两层以上的绝缘树脂组合物层形成的连接板，以及形成为在其绝缘树脂组合物层的厚度方向上形成的连接导体， 连接导体电路，并且使用多层布线板，半导体封装用基板和使用该连接基板的半导体封装，以及其制造方法。